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Kenzo K Ishida

from San Francisco, CA
Age ~71
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Also known as:
Ken Zo Ishida, Ken-Zo Ishida, Kunio Kenzo
Related to:
Shoya Ishida, 41Miyuki Ishida, 67Erina Ishida, 39Yuka Ishida
Connected to:
Asako Ishida, 44Benjamin T Ishida, 81Dennis P Ishida, 56Devin K Ishida, 55Guillermo Ishida, 54Jo M Ishida, 41Julius Ishida, 97Junya Ishida, 46Katsuhisa Ishida, 44Kazuko Ishida, 77

Kenzo Ishida Phones & Addresses

  • San Francisco, CA
  • Santa Clara, CA
  • 1250 45Th St STE 355, Emeryville, CA 94608 (408) 873-7747
  • 535 Pierce St, Albany, CA 94706
  • 7635 De Foe Dr, Cupertino, CA 95014 (408) 873-7747
  • Saratoga, CA
  • San Jose, CA
  • Alameda, CA
  • 7635 De Foe Dr, Cupertino, CA 95014 (408) 646-4821

Work

Company: Aidi corporation Jun 2004 Address: Tsukuba, Ibaraki, Japan Position: Ceo

Education

Degree: MS School / High School: Osaka University Graduate School 1976 to 1978 Specialities: Welding Engineering Material Science

Languages

Japanese • English

Industries

Semiconductors

Resumes

Resumes

Kenzo Ishida Photo 1

Corporate President & Ceo At Aidi Corporation

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Position:
CEO at AiDi Corporation
Location:
Ibaraki, Japan
Industry:
Semiconductors
Work:
AiDi Corporation - Tsukuba, Ibaraki, Japan since Jun 2004
CEO
JDS Uniphase - Materials & Asia Business Development 2002 - 2004
Sr. Director
Scion Photonics, Inc. - Milpitas, CA USA Oct 2000 - Apr 2002
Sr. Vice President & Chief Materials Officer
Intel Corporation - San Jose, CA USA Sep 2000 - Sep 2000
Senior Manager, Optical Component Operations
Intel Corporation - Santa Clara, CA USA Feb 2000 - Aug 2000
Director of Manufacturing Development, Display Technology Investment
Education:
Osaka University Graduate School 1976 - 1978
MS, Welding Engineering Material Science Osaka Institute of Technology 1972 - 1976
BS, Mechanical Engineering Material Science
Languages:
Japanese
English

Business Records

Name / Title
Company / Classification
Phones & Addresses
Kenzo Ishida
President
AIDI USA, INC
Nonclassifiable Establishments · Mfg Cordage/Twine
90 New Montgomery St, San Francisco, CA 94105
3140 De Ln Cruz Blvd, Santa Clara, CA 95054

Publications

Us Patents

Silent Heat Exchanger And Fan Assembly

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US Patent:
6422303, Jul 23, 2002
Filed:
Mar 14, 2000
Appl. No.:
09/524798
Inventors:
Kenzo Ishida - San Jose CA
Shinya Endo - Ibaraki-Ken, JP
Daryl J. Nelson - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
F28F 700
US Classification:
165 803, 16510433, 165185, 165135, 361 697, 361700, 257706, 257715
Abstract:
A heat dissipation device comprising a thermally conductive, hollow housing having a fan and an active anti-noise module disposed within the hollow housing. The hollow housing may include a plurality of fins disposed therein to increase the surface area for convective heat transfer. The heat dissipation device further may further include heat pipes for the transportation and dispersion of heat to and about an external surface of the hollow housing.

Transfer Molded Packages With Embedded Thermal Insulation

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US Patent:
6606425, Aug 12, 2003
Filed:
Mar 18, 2002
Appl. No.:
10/100277
Inventors:
Douglas E. Crafts - San Jose CA
Kenzo Ishida - Saratoga CA
David J. Chapman - San Jose CA
Duane Cook - San Jose CA
James F. Farrell - San Jose CA
Suresh Ramalingam - Fremont CA
Steven M. Swain - San Jose CA
Assignee:
JDS Uniphase Corporation - San Jose CA
International Classification:
G02B 612
US Classification:
385 14, 385129, 385130, 385 37, 385 92, 385 94
Abstract:
An optical component package, in which a transfer molded layer of material (e. g. , syntactic foam in one embodiment) is formed at least partially around, or entirely around, the optical component to provide structural and thermal insulation around the component. The optical component may be a planar lightwave circuit (PLC), with a protective passivation layer formed between the PLC and the layer of syntactic foam, to de-couple stresses and thermal transfer between the PLC and the layer of syntactic foam. Strengthening caps, fiber assemblies, and a heater may be provided with the PLC assembly, around which the layer of syntactic foam can also be formed. The protective passivation layer can also be formed between these structures and the syntactic foam; in one embodiment between at least two strengthening caps formed on opposing edges of the PLC. The disclosed package provides numerous structural, thermal and size benefits.

Package For Optical Components

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US Patent:
6664511, Dec 16, 2003
Filed:
Oct 28, 2002
Appl. No.:
10/281876
Inventors:
Douglas E. Crafts - San Jose CA
James F. Farrell - San Jose CA
Mark B. Farrelly - San Jose CA
Suresh Ramalingam - Fremont CA
Kenzo Ishida - San Jose CA
Assignee:
JDS Uniphase Corporation - San Jose CA
International Classification:
H05B 100
US Classification:
219209, 219210, 219520, 219385
Abstract:
A package for optical components includes an inner package enclosing the optical component, and an outer package enclosing the inner package. A heater may be disposed in the inner package proximate the optical component to control its temperature, and to maintain this temperature control, the outer package creates an isolated air pocket around the inner package, which thermally insulates the inner package from the outside environment. The outer package is formed of a material having low thermal conductivity, to promote this insulating function. This package is especially useful if the optical component comprises a planar light-wave circuit (PLC), e. g. an arrayed waveguide grating (AWG), which requires tight temperature control and structural integrity to maintain the integrity of the optical paths.

Precision Fiber Optic Alignment And Attachment Apparatus

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US Patent:
6665475, Dec 16, 2003
Filed:
Nov 30, 2001
Appl. No.:
10/001266
Inventors:
Kenzo Ishida - San Jose CA
Assignee:
JDS Uniphase Corporation - San Jose CA
International Classification:
G02B 630
US Classification:
385 49, 385 50, 385 51, 385 52
Abstract:
A groove assembly for holding at least one fiber optic. The assembly includes a base, a cover and a small carrier disposed between the base and the cover. The carrier has at least one groove. At least one fiber optic is disposed in this groove and terminates at an edge surface of the carrier. The base and cover have respective edge surfaces serving as attachment surfaces for attachment of the assembly to a planar lightwave circuit (PLC). The PLC has at least one waveguide terminating at an edge, to which the fiber requires alignment. The base and/or cover are preferably formed from a material enabling attachment to the PLC, e. g. , transparent to energy used for curing an adhesive. The carrier is formed from material enabling a substantially more precise formation of the grooves, e. g. , silicon.

Compact, Low Insertion Loss, High Yield Arrayed Waveguide Grating

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US Patent:
6697553, Feb 24, 2004
Filed:
Feb 15, 2002
Appl. No.:
10/077581
Inventors:
Jyoti Kiron Bhardwaj - Cupertino CA
Robert James Brainard - Sunnyvale CA
David J. Chapman - San Jose CA
Douglas E. Crafts - San Jose CA
David Dougherty - Sunnyvale CA
Erik W. Egan - Oakland CA
James F. Farrell - San Jose CA
Mark B. Farrelly - San Jose CA
Niranjan Gopinathan - Santa Clara CA
Kenzo Ishida - Saratoga CA
David K. Nakamoto - Sunnyvale CA
Thomas Thuan Nguyen - San Jose CA
Suresh Ramalingam - Fremont CA
Steven M. Swain - San Jose CA
Sanjay M. Thekdi - Santa Clara CA
Anantharaman Vaidyanathan - San Jose CA
Hiroaki Yamada - San Jose CA
Yingchao Yan - Milpitas CA
Assignee:
JDS Uniphase Corporation - San Jose CA
International Classification:
G02B 634
US Classification:
385 37, 385 24, 385 46, 385 43
Abstract:
A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e. g. , width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).

Apparatus And Method For Warpage Compensation Of A Display Panel Substrate Assembly

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US Patent:
6798137, Sep 28, 2004
Filed:
Nov 22, 2002
Appl. No.:
10/302282
Inventors:
Kenzo Ishida - Cupertino CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01J 162
US Classification:
313512, 313504, 313505
Abstract:
An apparatus and method for warpage compensation of a display panel substrate assembly are described. A method and apparatus for warpage compensation of a display panel substrate assembly are described. In one embodiment, the method includes the selection of a substrate having a substrate warpage level exceeding a warpage tolerance level. Once selected, a plurality of conductive bumps are formed over an area of the selected substrate. Once formed, a thermal process is applied to the plurality of conductive bumps to obtain a virtual plane over the area of the selected substrate have a coplanarity level below a coplanarity specification level. As such, utilizing embodiments of the present invention, lower cost substrates with substandard warpage levels may be utilized to form OLED panel substrate assemblies when compensated utilizing embodiments of the present invention.

Apparatus And Method For Warpage Compensation Of A Display Panel Substrate Assembly

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US Patent:
7171743, Feb 6, 2007
Filed:
May 7, 2004
Appl. No.:
10/841350
Inventors:
Kenzo Ishida - Cupertino CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H05K 3/30
US Classification:
29832, 29840, 29842, 29843
Abstract:
An apparatus and method for warpage compensation of a display panel substrate assembly are described. A method and apparatus for warpage compensation of a display panel substrate assembly are described. In one embodiment, the method includes the selection of a substrate having a substrate warpage level exceeding a warpage tolerance level. Once selected, a plurality of conductive bumps are formed over an area of the selected substrate. Once formed, a thermal process is applied to the plurality of conductive bumps to obtain a virtual plane over the area of the selected substrate have a coplanarity level below a coplanarity specification level. As such, utilizing embodiments of the present invention, lower cost substrates with substandard warpage levels may be utilized to form OLED panel substrate assemblies when compensated utilizing embodiments of the present invention.

Low Loss Funnel-Type Plc Optical Splitter With Input Cladding Mode Absorption Structure And/Or Output Segmented Taper Structure

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US Patent:
7330620, Feb 12, 2008
Filed:
Feb 16, 2007
Appl. No.:
11/675896
Inventors:
Kenzo Ishida - Albany CA, US
Alan Tafapolsky - Piedmont CA, US
Takaharu Fujiyama - Albany CA, US
Assignee:
Aidi Corporation - Ibaraki
International Classification:
G02B 6/02
G02B 6/10
US Classification:
385 43, 385 45, 385129
Abstract:
A funnel-type planar lightwave circuit (PLC) optical splitter having an input optical waveguide, a slab waveguide receiving the input optical signal from the input optical waveguide, and output waveguides projecting from the slab region. The region connecting the slab waveguide to the output waveguides is characterized by a segmented taper structure. In another additional, or alternative aspect of the present invention, a cladding mode absorption region runs along either or both sides of the input optical waveguide. A funnel-type splitter with both a cladding mode absorption region and a segmented taper structure provides a “super” low loss splitter design, when considering both insertion loss and polarization dependent loss. Advantageously, the disclosed funnel-type PLC splitter does not require a quartz substrate due to its very low PDL, and a silicon substrate can be used. Silicon substrates are known to be lower cost, with a higher resistance to fracture.
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Kenzo K Ishida from San Francisco, CA, age ~71 Get Report