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Kenneth J Reyer

from Stormville, NY
Age ~61
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Also known as:
Kenneth K Reyer, Ken Reyer
Phone and address:
175 Judith Dr, Stormville, NY 12582
(845) 221-1436
Related to:
Erika N Reyer, 33Katherine ReyerChristopher M Reyer, 29Donna A Reyer, 59
Connected to:
Jessica R Reyer, 43Kristin D Reyer, 38Patty E Reyer, 94Sarah M Reyer, 71Stephen B Reyer, 59Tina M Reyero, 48Travis Reyersbach, 29Constant C Reyerse, 73Chris Reyerson, 53Jesse S Reyerson, 43

Kenneth Reyer Phones & Addresses

  • 175 Judith Dr, Stormville, NY 12582 (845) 221-1436
  • 25 Judith Dr, Stormville, NY 12582 (845) 221-1436
  • 1802 Ravinia Cir, Venice, FL 34292 (941) 483-1980
  • 402 Commons Way, Fishkill, NY 12524 (845) 897-4102
  • 402 Commons Way UNIT F, Fishkill, NY 12524 (845) 897-4102
  • Ridgewood, NY
  • Wappingers Falls, NY

Skills

Microsoft Word • Powerpoint • Outlook • Microsoft Office • Customer Service • Microsoft Excel • Budgets • Process Scheduler • Construction • Account Management • Windows

Resumes

Resumes

Kenneth Reyer Photo 1

Kenneth Reyer

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Skills:
Microsoft Word
Powerpoint
Outlook
Microsoft Office
Customer Service
Microsoft Excel
Budgets
Process Scheduler
Construction
Account Management
Windows

Publications

Us Patents

Apparatus And Method For Implementing Multiple Memory Redundancy With Delay Tracking Clock

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US Patent:
7068554, Jun 27, 2006
Filed:
Feb 9, 2005
Appl. No.:
11/054272
Inventors:
James W. Dawson - Poughkeepsie NY, US
Thomas J. Knips - Wappingers Falls NY, US
Donald W. Plass - Poughkeepsie NY, US
Kenneth J. Reyer - Stormville NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 7/00
US Classification:
365200, 36518907, 365233
Abstract:
A memory redundancy control apparatus includes a static compare stage configured to compare bits of a requested memory address to corresponding fuse information bits representing a defective memory address. A dynamic stage is configured to receive outputs of the static compare stage, with an output of the dynamic stage being precharged so as to initially deactivate primary subarray decoding circuitry. The dynamic stage is further triggered by a clock signal thereto. Upon activation of the clock signal, the output of the dynamic stage remains precharged whenever a match exists between the requested memory address and the defective memory address, and the output of the dynamic stage is discharged whenever a mismatch exists between the requested memory address and the defective memory address. A delay tracking clock generator is configured to generate a delay tracking clock signal with respect to the dynamic stage, to gate the output of the dynamic stage to spare subarray decoding circuitry, wherein the spare subarray decoding circuitry is activated whenever the output of the dynamic stage remains precharged following activation of the clock signal.

High Density Bitline Selection Apparatus For Semiconductor Memory Devices

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US Patent:
7099206, Aug 29, 2006
Filed:
Jan 28, 2005
Appl. No.:
11/046101
Inventors:
James W. Dawson - Poughkeepsie NY, US
Donald W. Plass - Poughkeepsie NY, US
Kenneth J. Reyer - Stormville NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 7/00
US Classification:
365190, 365 63, 365188
Abstract:
A bitline selection apparatus for a semiconductor memory device includes a first local bitline pair and a second local bitline pair selectively coupled to a global bitline pair, each of the first and second local bitline pairs including a true bitline and a complementary bitline. Each of the true bitlines is selectively coupled to a common true node through an n-type pass device and a p-type pass device in parallel therewith, and each of the complementary bitlines is selectively coupled to a common complementary node through an n-type pass device and a p-type pass device in parallel therewith.

Fast Pulse Powered Nor Decode Apparatus For Semiconductor Devices

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US Patent:
7176725, Feb 13, 2007
Filed:
Feb 4, 2005
Appl. No.:
11/050895
Inventors:
James W. Dawson - Poughkeepsie NY, US
Donald W. Plass - Poughkeepsie NY, US
Kenneth J. Reyer - Stormville NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 19/094
H03K 19/096
US Classification:
326105, 326 98
Abstract:
A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and the dynamic stage are controlled by a clock signal so as to enable a self-timed evaluation of the pulse-powered stage with a clocked enablement of the dynamic stage.

Write Control Circuitry And Method For A Memory Array Configured With Multiple Memory Subarrays

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US Patent:
7283417, Oct 16, 2007
Filed:
Feb 9, 2005
Appl. No.:
11/054059
Inventors:
John D. Davis - Wallkill NY, US
Paul A. Bunce - Poughkeepsie NY, US
Donald W. Plass - Poughkeepsie NY, US
Kenneth J. Reyer - Stormville NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 8/00
US Classification:
36523003, 365156, 365154
Abstract:
Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.

Clock Control Method And Apparatus For A Memory Array

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US Patent:
7299374, Nov 20, 2007
Filed:
Feb 3, 2005
Appl. No.:
11/050580
Inventors:
James W. Dawson - Poughkeepsie NY, US
Paul A. Bunce - Poughkeepsie NY, US
Donald W. Plass - Poughkeepsie NY, US
Kenneth J. Reyer - Stormville NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1/08
G06F 1/04
US Classification:
713501, 713500, 713600
Abstract:
A clock control method and apparatus are provided employing a clock control circuit which generates an array clock for a memory array from a system clock and a reset control signal. The reset control signal is one of a plurality of input control signals to the clock control circuit. When the system clock is below a predefined frequency threshold, the reset control signal is an array tracking reset signal, wherein the active pulse width of the array clock is system clock frequency independent, and when the system clock is above the predefined frequency threshold, the reset control signal is a mid-cycle reset signal, meaning that the active pulse width of the array clock is system clock frequency dependent. A bypass signal is provided as a third input control signal, which when active causes the clock control circuit to output an array clock which mirrors the system clock.

Abist Data Compression And Serialization For Memory Built-In Self Test Of Sram With Redundancy

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US Patent:
7380191, May 27, 2008
Filed:
Feb 9, 2005
Appl. No.:
11/054566
Inventors:
James W. Dawson - Poughkeepsie NY, US
Thomas J. Knips - Wappingers Falls NY, US
Donald W. Plass - Poughkeepsie NY, US
Kenneth J. Reyer - Stormville NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/28
G01C 29/00
US Classification:
714733, 714736, 714718
Abstract:
A method and apparatus for implementing ABIST data compression and serialization for memory built-in self test of SRAM with redundancy. The method includes providing detection signals asserted for one failing data out, two failing data outs, and greater than two failing data outs. The method also includes individually encoding the failing bit position of each corresponding failing data out with a binary representation value corresponding therewith. The method further includes serializing results of the providing detection signals and the individually encoding, and transmitting results of the serializing to a redundancy support register function on a single fail buss.

Write Control Circuitry And Method For A Memory Array Configured With Multiple Memory Subarrays

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US Patent:
7471590, Dec 30, 2008
Filed:
Jun 14, 2007
Appl. No.:
11/762833
Inventors:
John D. Davis - Wallkill NY, US
Paul A. Bunce - Poughkeepsie NY, US
Donald W. Plass - Poughkeepsie NY, US
Kenneth J Reyer - Stormville NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 8/00
US Classification:
36523006, 36518909, 365226, 36523003
Abstract:
Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.

Write Control Method For A Memory Array Configured With Multiple Memory Subarrays

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US Patent:
7688650, Mar 30, 2010
Filed:
Jun 16, 2008
Appl. No.:
12/139675
Inventors:
John D. Davis - Wallkill NY, US
Paul A. Bunce - Poughkeepsie NY, US
Donald W. Plass - Poughkeepsie NY, US
Kenneth J. Reyer - Stormville NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 7/00
G11C 7/22
US Classification:
36518916, 365154, 365156, 36523003, 36523006
Abstract:
Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.
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Kenneth J Reyer from Stormville, NY, age ~61 Get Report