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Ken Takeuchi

from Stanford, CA
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Related to:
Yukino Takeuchi
Connected to:
Chikako Takeuchi, 65Dana M Takeuchi, 80Eileen N Takeuchi, 71Elizabeth G Takeuchi, 80Hideyuki Takeuchi, 62Hiroyuki Takeuchi, 64Jane K Takeuchi, 89Jun Takeuchi, 56Kenta Takeuchi, 41Kentaro Takeuchi, 55

Ken Takeuchi Phones & Addresses

  • Stanford, CA
  • 4 Foxwood Sq S, Westwood, NJ 07675 (201) 750-2047
  • Old Tappan, NJ

Business Records

Name / Title
Company / Classification
Phones & Addresses
Ken Takeuchi
Chief Technology Engineer
Bridge Multimedia Corp
Research · Production of Video · Multimedia (Manufacturers) · All Other Publishers
49 W 27 St #901, New York, NY 10001
Matt Kaplowitz 49 W 27 St / 8, New York, NY 10001
49 W 27 St / 8, New York, NY 10001
(212) 213-3740, (212) 213-9715

Publications

Us Patents

Semiconductor Memory Device Having A Plurality Of Chips And Capability Of Outputting A Busy Signal

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US Patent:
6680858, Jan 20, 2004
Filed:
Jun 28, 2002
Appl. No.:
10/185645
Inventors:
Hiroshi Nakamura - Fujisawa, JP
Kenichi Imamiya - Tokyo, JP
Ken Takeuchi - Stanford CA
Assignee:
Kabushiki Kaisha Toshiba - Tokyo
International Classification:
G11C 506
US Classification:
365 63, 365 51, 36518907, 36518908, 36523003
Abstract:
One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Semiconductor Memory Device Having A Plurality Of Chips And Capability Of Outputting A Busy Signal

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US Patent:
6990003, Jan 24, 2006
Filed:
Jan 8, 2004
Appl. No.:
10/754993
Inventors:
Hiroshi Nakamura - Fujisawa, JP
Kenichi Imamiya - Tokyo, JP
Ken Takeuchi - Stanford CA, US
Assignee:
Kabushiki Kaisha Toshiba - Tokyo
International Classification:
G11C 5/06
US Classification:
365 63, 365 51, 36518907, 36518908, 36523003
Abstract:
One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates, a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Semiconductor Memory Device Having A Plurality Of Chips And Capability Of Outputting A Busy Signal

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US Patent:
7522442, Apr 21, 2009
Filed:
Oct 5, 2007
Appl. No.:
11/973274
Inventors:
Hiroshi Nakamura - Fujisawa, JP
Kenichi Imamiya - Tokyo, JP
Ken Takeuchi - Stanford CA, US
Assignee:
Kabushiki Kaisha Toshiba - Tokyo
International Classification:
G11C 5/06
US Classification:
365 63, 365 51, 365 52, 365191, 365200
Abstract:
One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Semiconductor Memory Device Having A Plurality Of Chips And Capability Of Outputting A Busy Signal

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US Patent:
7542323, Jun 2, 2009
Filed:
Sep 24, 2004
Appl. No.:
10/949274
Inventors:
Hiroshi Nakamura - Fujisawa, JP
Kenichi Imamiya - Tokyo, JP
Ken Takeuchi - Stanford CA, US
Assignee:
Kabushiki Kaisha Toshiba - Tokyo
International Classification:
G11C 5/06
US Classification:
365 63, 36518905, 36518907, 365191
Abstract:
One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Semiconductor Memory Device Having A Plurality Of Chips And Capability Of Outputting A Busy Signal

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US Patent:
7596042, Sep 29, 2009
Filed:
Oct 2, 2007
Appl. No.:
11/906379
Inventors:
Hiroshi Nakamura - Fujisawa, JP
Kenichi Imamiya - Tokyo, JP
Ken Takeuchi - Stanford CA, US
Assignee:
Kabushiki Kaisha Toshiba - Tokyo
International Classification:
G11C 7/00
US Classification:
365191, 36518515, 36518516, 365201
Abstract:
One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Semiconductor Memory Device Having A Plurality Of Chips And Capability Of Outputting A Busy Signal

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US Patent:
7751259, Jul 6, 2010
Filed:
Sep 27, 2007
Appl. No.:
11/904560
Inventors:
Hiroshi Nakamura - Fujisawa, JP
Kenichi Imamiya - Tokyo, JP
Ken Takeuchi - Stanford CA, US
Assignee:
Kabushiki Kaisha Toshiba - Tokyo
International Classification:
G11C 7/00
US Classification:
365191, 36518907, 36518911
Abstract:
One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Semiconductor Memory Device Having A Plurality Of Chips And Capability Of Outputting A Busy Signal

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US Patent:
7933134, Apr 26, 2011
Filed:
Sep 27, 2007
Appl. No.:
11/904565
Inventors:
Hiroshi Nakamura - Fujisawa, JP
Kenichi Imamiya - Tokyo, JP
Ken Takeuchi - Stanford CA, US
Assignee:
Kabushiki Kaisha Toshiba - Tokyo
International Classification:
G11C 5/06
US Classification:
365 63, 365191, 365201
Abstract:
One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Semiconductor Memory Device Having A Plurality Of Chips And Capability Of Outputting A Busy Signal

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US Patent:
8331124, Dec 11, 2012
Filed:
Mar 25, 2011
Appl. No.:
13/071729
Inventors:
Hiroshi Nakamura - Fujisawa, JP
Kenichi Imamiya - Tokyo, JP
Ken Takeuchi - Stanford CA, US
Assignee:
Kabushiki Kaisha Toshiba - Tokyo
International Classification:
G11C 5/06
US Classification:
365 63, 36518905, 36518907, 365191
Abstract:
One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Wikipedia References

Ken Takeuchi Photo 2

Ken Takeuchi

About:
Born:

20 February 1978 • Tokyo , Japan

Work:
Position:

Japanese voice actor

Education:

Takeuchi learned voice acting at the Institute of Japan Narration Act..

Skills & Activities:

In 2000, he debuted as a main character in the video game " Photogenic ", and in 2003, he played one of the main characters, Ranmaru Miura, in " Dear Boys " ( also known as " Hoop Days " ).

Wikipedia

Ken Takeuchi

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Ken Takeuchi ( , Takeuchi Ken, born February 20, 1978) is a Japanese voice actor who works for Arts Vision. Takeuchi learned voice acting in Institute ...
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Ken Takeuchi from Stanford, CA Get Report