Search

Kelly W Kyler

from Mesa, AZ
Age ~67
Get Report
Also known as:
Kelly Wayne Kyler, Kelly Te Kyler, Kelly Q Kyler, Kelly M Kyler, Kelley W Kyler
Phone and address:
8904 Minton St, Mesa, AZ 85207
(480) 354-0463
Related to:
Bryan McquayRoss KylerKatelyn K Coleman, 35Keston Wing, 37Robin D Kyler
Connected to:
Annalisa J Kyler, 45Eric S Kyler, 48Lee Kyler, 39Lori K Kyler, 63Michelle A Kyler, 59Sharon R Kyler, 60Yvonne E Kyler, 95Alvinakka Kyles, 43Arlita M Kyles, 60Brent Kyles, 41

Kelly Kyler Phones & Addresses

  • 8904 Minton St, Mesa, AZ 85207 (480) 354-0463
  • 710 Winthrop, Mesa, AZ 85204
  • 2303 Garnet Ave, Mesa, AZ 85204 (480) 507-7883
  • Show Low, AZ
  • Snowflake, AZ
  • White Mountain Lake, AZ
  • 195 Cottonwood St, Chandler, AZ 85225
  • Gilbert, AZ
  • Orem, UT
  • Salt Lake City, UT
  • Englewood, CO
  • Maricopa, AZ
  • 8904 E Minton St, Mesa, AZ 85207 (480) 375-8438

Work

Company: Everspin/freescale/motorola - Chandler, AZ Jun 1987 Position: Process engineer

Education

School / High School: Brigham Young University- Provo, UT 1984 Specialities: BS in Chemistry

Emails

k***r@motorola.com

Resumes

Resumes

Kelly Kyler Photo 1

Kelly Kyler

View page
Location:
8904 east Minton St, Mesa, AZ 85207
Industry:
Semiconductors
Work:
Intel Corporation
Iq
Air Products Jan 2015 - Aug 2017
Senior Process Cleanroom Supervisor
Compound Photonics Dec 2013 - Apr 2015
Process Development Engineer
Motorola Labs Motorola Aug 1997 - Sep 2013
Principal Process Engineer
Motorola Jul 1995 - Aug 1997
Senior Process Engineer Motorola Labs
Education:
Brigham Young University 1984 - 1987
Bachelors, Bachelor of Science, Chemistry
Skills:
Jmp
Cmos
Spc
Manufacturing
Design of Experiments
Failure Analysis
Product Development
Six Sigma
Metrology
Characterization
Semiconductors
R
Thin Films
Analog
Cross Functional Team Leadership
Lean Manufacturing
Engineering
Sensors
Testing
Simulations
Kelly Kyler Photo 2

Kelly Kyler

View page
Location:
Mesa, AZ
Industry:
Semiconductors
Work:
Compound Photonics
Process Engineer
Education:
Brigham Young University
Bachelors, Bachelor of Science, Chemistry
Skills:
Six Sigma
Engineering Management
Pvd
Photolithography
Electronics
Business Development
Jmp
Thin Films
Cmos
Manufacturing
Cvd
Failure Analysis
Semiconductors
Process Engineering
Plasma Etch
R&D
Process Simulation
Silicon
Yield
Ic
Kelly Kyler Photo 3

Process And Development Engineer

View page
Location:
1347 north Alma School Rd, Chandler, AZ 85224
Industry:
Semiconductors
Work:
Everspin Technologies
Process and Development Engineer
Kelly Kyler Photo 4

Kelly Kyler Mesa, AZ

View page
Work:
Everspin/Freescale/Motorola
Chandler, AZ
Jun 1987 to Sep 2013
Process Engineer
Education:
Brigham Young University
Provo, UT
1984 to 1987
BS in Chemistry

Business Records

Name / Title
Company / Classification
Phones & Addresses
Kelly W Kyler
Manager
SMART MONEY STRATEGIES, LLC
8904 E Minton St, Mesa, AZ 85207
Kelly W Kyler
Manager
HAMAKUA DREAM, LLC
Business Services at Non-Commercial Site
8904 E Minton St, Mesa, AZ 85207
Kelly L. Kyler
NORTH CENTRAL PROPANE, LTD
Kelly W Kyler
Principal
HEART-AGE LLC
Nonclassifiable Establishments
8904 E Minton St, Mesa, AZ 85207

Publications

Us Patents

Plasma Processing Method

View page
US Patent:
6334929, Jan 1, 2002
Filed:
Jul 29, 1994
Appl. No.:
08/282295
Inventors:
Kelly W. Kyler - Chandler AZ
Fred Clayton - Mesa AZ
James H. Williams - Tempe AZ
Jaeshin Cho - Chandler AZ
Craig L. Jasper - Phoenix AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
B44C 122
US Classification:
156625
Abstract:
A process for improving uniformity across the surface of a substrate during a plasma process such as plasma etching. A conductive plane is formed at the back surface of the substrate. A plasma process is then performed to the front surface of the substrate. The conductive plane may then be removed upon completion of the plasma process and before final processing steps.

High Density Mram Cell Array

View page
US Patent:
6365419, Apr 2, 2002
Filed:
Aug 28, 2000
Appl. No.:
09/649114
Inventors:
Mark Durlam - Chandler AZ
Mark DeHerrera - Tempe AZ
Eugene Chen - Gilbert AZ
Saied Tehrani - Tempe AZ
Gloria Kerszykowski - Fountain Hills AZ
Peter K. Naji - Phoenix AZ
Jon Slaughter - Tempe AZ
Kelly W. Kyler - Mesa AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2100
US Classification:
438 3, 438 57, 257421
Abstract:
A method of fabricating an MRAM cell includes providing an isolation transistor on a semiconductor substrate and forming an interconnect stack on the substrate in communication with one terminal of the transistor. A via is formed on the upper end of the stack so as to extend from a position below the digit line to a position above the digit line. The via also extends above the upper surface of a dielectric layer to provide an alignment key. A MTJ memory cell is positioned on the upper surface in contact with the via, and the ends of a free layer of magnetic material are spaced from the ends of a pinned edge of magnetic material by using sidewall spacers and selective etching.

Magnetoresistive Random Access Memory Device And Method Of Fabrication Thereof

View page
US Patent:
6518071, Feb 11, 2003
Filed:
Mar 28, 2002
Appl. No.:
10/109429
Inventors:
Mark A. Durlam - Chandler AZ
Mark F. Deherrera - Tempe AZ
Kelly W. Kyler - Mesa AZ
Brian R. Butcher - Gilbert AZ
Gregory W. Grynkewich - Gilbert AZ
Steven M. Smith - Gilbert AZ
Charles Snyder - Gilbert AZ
Jon M. Slaughter - Tempe AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2100
US Classification:
438 3, 438 43
Abstract:
A method of fabricating a MRAM device with a taper comprising the steps of providing a substrate, forming a dielectric region with positioned on the substrate, patterning and isotropically etching through the dielectric region to the substrate to form a trench, depositing the MRAM device within the trench wherein the MRAM device includes a first ferromagnetic region with a width positioned on the substrate, a non-ferromagnetic spacer layer with a width positioned on the first ferromagnetic region, and a second ferromagnetic region with a width positioned on the non-ferromagnetic spacer layer wherein the taper is formed by making the width of the first ferromagnetic region greater than the width of the non-ferromagnetic spacer layer, and the width of the non-ferromagnetic spacer layer greater than the width of the second ferromagnetic region so that the first ferromagnetic region is separated from the second ferromagnetic region.

Method Of Fabricating A Self-Aligned Magnetic Tunneling Junction And Via Contact

View page
US Patent:
6783994, Aug 31, 2004
Filed:
Apr 26, 2002
Appl. No.:
10/133136
Inventors:
Nicholas D. Rizzo - Gilbert AZ
Kelly W. Kyler - Mesa AZ
Gregory W. Grynkewich - Gilbert AZ
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 2100
US Classification:
438 3, 365 50, 365158, 365173, 438739
Abstract:
A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a first conductive layer positioned on the substrate, forming a conductive material stack region with a flat surface, the conductive material stack region being positioned on a portion of the first conductive layer, and forming a magnetoresistive random access memory device positioned on the flat surface of the conductive material stack region, the magnetoresistive random access memory device being isolated from the first conductive layer and subsequent layers grown thereon.

Method Of Fabricating A Self-Aligned Via Contact For A Magnetic Memory Element

View page
US Patent:
6812040, Nov 2, 2004
Filed:
Mar 12, 2002
Appl. No.:
10/095816
Inventors:
Kelly Kyler - Mesa AZ
Saied N. Tehrani - Tempe AZ
John J. Durso - Chandler AZ
Gregory W. Grynkewich - Gilbert AZ
Mark A. Durlam - Chandler AZ
Brian Butcher - Gilbert AZ
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 2100
US Classification:
438 3, 438612, 365158
Abstract:
A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a conductive layer positioned on the substrate, forming a magnetoresistive random access memory device positioned on conductive layer, forming a metal cap on the magnetoresistive random access memory device, and electroless plating a bump metal layer on the metal cap. The bump metal layer acts as a self-aligned via for a bit line subsequently formed thereon.

Method Of Fabricating A Magnetic Element With Insulating Veils

View page
US Patent:
6835423, Dec 28, 2004
Filed:
Jan 22, 2003
Appl. No.:
10/349702
Inventors:
Eugene Youjun Chen - Gilbert AZ
Mark Durlam - Chandler AZ
Saied N. Tehrani - Tempe AZ
Mark DeHerrera - Tempe AZ
Gloria Kerszykowski - Fountain Hills AZ
Kelly Wayne Kyler - Mesa AZ
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H05H 100
US Classification:
427539, 427123, 427130, 427131, 427132, 427258, 427261, 4273831, 427404, 427547, 427598
Abstract:
An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element ( ) including a first electrode ( ), a second electrode ( ) and a spacer layer ( ). The first electrode ( ) and the second electrode ( ) include ferromagnetic layers ( ). A spacer layer ( ) is located between the ferromagnetic layer ( ) of the first electrode ( ) and the ferromagnetic layer ( ) of the second electrode ( ) for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers ( ). The device includes insulative veils ( ) characterized as electrically isolating the first electrode ( ) and the second electrode ( ), the insulative veils ( ) including non-magnetic and insulating dielectric properties. Additionally disclosed is a method of fabricating the magnetic element ( ) with insulative veils ( ) that have been transformed from having conductive properties to insulative properties through oxygen plasma ashing techniques.

Methods For Contacting Conducting Layers Overlying Magnetoelectronic Elements Of Mram Devices

View page
US Patent:
6881351, Apr 19, 2005
Filed:
Apr 22, 2003
Appl. No.:
10/421096
Inventors:
Gregory W. Grynkewich - Gilbert AZ, US
Brian R. Butcher - Gilbert AZ, US
Mark A. Durlam - Chandler AZ, US
Kelly Kyler - Mesa AZ, US
Charles A. Synder - Gilbert AZ, US
Kenneth H. Smith - Chandler AZ, US
Clarence J. Tracy - Tempe AZ, US
Richard Williams - Chandler AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L021/00
US Classification:
216 22, 216 41, 216 47, 216 72, 216 88, 438 3, 438692, 438696, 438700, 205663
Abstract:
A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.

Cladded Conductor For Use In A Magnetoelectronics Device And Method For Fabricating The Same

View page
US Patent:
6885074, Apr 26, 2005
Filed:
Nov 27, 2002
Appl. No.:
10/306250
Inventors:
Mark A. Durlam - Chandler AZ, US
Jeffrey H. Baker - Chandler AZ, US
Brian R. Butcher - Gilbert AZ, US
Mark F. Deherrera - Tempe AZ, US
John J. D'Urso - Chandler AZ, US
Earl D. Fuchs - Phoenix AZ, US
Gregory W. Grynkewich - Gilbert AZ, US
Kelly W. Kyler - Mesa AZ, US
Jaynal A. Molla - Gilbert AZ, US
J. Jack Ren - Phoenix AZ, US
Nicholas D. Rizzo - Gilbert AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L029/82
H01L027/14
US Classification:
257422, 257252
Abstract:
A method for fabricating a cladded conductor () for use in a magnetoelectronics device is provided. The method includes providing a substrate () and forming a conductive barrier layer () overlying the substrate (). A dielectric layer () is formed overlying the conductive barrier layer () and a conducting line () is formed within a portion of the dielectric layer (). The dielectric layer () is removed and a flux concentrator () is formed overlying the conducting line ().
Control profile
Kelly W Kyler from Mesa, AZ, age ~67 Get Report