Keith R Schakel

6546478, Apr 8, 2003

Oct 14, 1999

09/418098

James B. Keller - Palo Alto CA
Puneet Sharma - Singapore, SG
Keith R. Schakel - San Jose CA
Francis M. Matus - Sunnyvale CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 938

712204, 712210, 712213, 712237

A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides alignment information for the instruction beginning at the fetch address, as well as one or more additional instructions subsequent to that instruction. The alignment information may be, for example, instruction pointers, each of which directly locates a corresponding instruction within a plurality of instruction bytes fetched in response to the fetch address. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Furthermore, each entry may store additional information regarding the terminating instruction within the entry. In one embodiment, the additional information includes an indication of the branch displacement when the terminating instruction is a branch instruction.

6622237, Sep 16, 2003

Jan 3, 2000

09/476192

James B. Keller - Palo Alto CA
Thomas S. Green - Sunnyvale CA
Wei-Han Lien - Sunnyvale CA
Ramsey W. Haddad - Cupertino CA
Keith R. Schakel - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 900

712216, 712214, 712 23

A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor is trained with information for a particular load and store in response to executing the load and store and detecting the interference. Additionally, the STLF predictor may be untrained (e. g. information for a particular load and store may be deleted) if a load is indicated by the STLF predictor as dependent upon a particular store and the dependency does not actually occur. In one implementation, the STLF predictor records at least a portion of the PC of a store which interferes with the load in a first table indexed by the load PC. A second table maintains a corresponding portion of the store PCs of recently dispatched stores, along with tags identifying the recently dispatched stores.

6636959, Oct 21, 2003

Oct 14, 1999

09/416275

James B. Keller - Palo Alto CA
Puneet Sharma - Singapore, SG
Keith R. Schakel - San Jose CA
Francis M. Matus - Sunnyvale CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 938

712204, 712206, 712210

A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides information for the instruction beginning at the fetch address, as well as alignment information for up to one or more additional instructions subsequent to that instruction. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Since the line predictor provides alignment information from one entry per fetch, the line predictor may provide a flow control mechanism for the initial portion of the pipeline within a microprocessor. Each entry may store combinations of instructions which the hardware within the pipeline may handle without creating stalls resulting from the combinations.

6647490, Nov 11, 2003

Oct 14, 1999

09/419832

James B. Keller - Palo Alto CA
Puneet Sharma - Singapore, SG
Keith R. Schakel - San Jose CA
Francis M. Matus - Sunnyvale CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 938

712233, 712237

A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides alignment information for the instruction beginning at the fetch address, as well as one or more additional instructions subsequent to that instruction. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Additionally, each entry may include a link to another entry storing instruction pointers to the next instructions within the predicted instruction stream, and a next fetch address corresponding to the first instruction within the next entry. The next fetch address may be provided to the instruction cache to fetch the corresponding instruction bytes. If the terminating instruction within the entry is a branch instruction, the line predictor is trained with respect to the next fetch address (and next index within the line predictor, which provides the link to the next entry).

6687789, Feb 3, 2004

Jan 3, 2000

09/476577

James B. Keller - Palo Alto CA
Keith R. Schakel - San Jose CA
Puneet Sharma - Singapore, SG

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1200

711128, 711137, 711156, 711125

A cache is coupled to receive an input address and a corresponding way prediction. The cache provides output bytes in response to the predicted way (instead of, performing tag comparisons to select the output bytes). Furthermore, a tag may be read from the predicted way and only partial tags are read from the non-predicted ways. The tag is compared to the tag portion of the input address, and the partial tags are compared to a corresponding partial tag portion of the input address. If the tag matches the tag portion of the input address, a hit in the predicted way is detected and the bytes provided in response to the predicted way are correct. If the tag does not match the tag portion of the input address, a miss in the predicted way is detected. If none of the partial tags match the corresponding partial tag portion of the input address, a miss in the cache is determined. On the other hand, if one or more of the partial tags match the corresponding partial tags portion of the input address, the cache searches the corresponding ways to determine whether or not the input address hits or misses in the cache.

7215680, May 8, 2007

May 13, 2002

10/144187

Rodney N. Mullendore - San Jose CA, US
Stuart F. Oberman - Sunnyvale CA, US
Anil Mehta - Milpitas CA, US
Keith Schakel - San Jose CA, US
Kamran Malik - San Jose CA, US

Nishan Systems, Inc. - San Jose CA

H04L 12/56

370412

A system and method for enabling a network switch to transmit queued packets to a device when opened by the device, and thus to utilize the Fibre Channel Arbitrated Loop (FC-AL) in full-duplex mode when possible. The switch may include a plurality of queues each associated with a device on the FC-AL for queuing incoming packets for the device. The switch may determine a next non-empty queue, open the device associated with the queue, and send packets to the device. The device may send packets to the switch concurrently with receiving packets from the switch, thus utilizing the FC-AL in full-duplex mode. When a device opens the switch to transmit packets to the switch, the switch may determine if there are packets for the device in the queue and, if so, send packets to the device concurrently with receiving packets from the device, thus utilizing the FC-AL in full-duplex mode.

7227841, Jun 5, 2007

May 13, 2002

10/144081

Rodney N. Mullendore - San Jose CA, US
Stuart F. Oberman - Sunnyvale CA, US
Anil Mehta - Milpitas CA, US
Keith Schakel - San Jose CA, US
Kamran Malik - San Jose CA, US

Nishan Systems, Inc. - Broomfield CO

G01R 31/08

370230

A system and method for input thresholding packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Packets entering the network switch may be assigned to one of a plurality of threshold groups and to one of a plurality of flows within the threshold group. In one embodiment, each threshold group may be divided into a plurality of levels of operation. As resources are allocated or freed by the threshold group, the threshold group may dynamically move up or down in the levels of operation. Within each level, one or more different values may be used as level boundaries and resource limits for flows within the threshold group. In one embodiment, programmable registers may be used to store these values.

7283556, Oct 16, 2007

Jul 31, 2002

10/209158

Rodney N. Mullendore - San Jose CA, US
Stuart F. Oberman - Sunnyvale CA, US
Anil Mehta - Milpitas CA, US
Keith Schakel - San Jose CA, US
Kamran Malik - San Jose CA, US

Nishan Systems, Inc. - Broomfield CO

H04L 12/43

370458, 370442

A system and method for managing the allocation of Time Division Multiplexing (TDM) timeslots in a network switch. The network switch may use a TDM cycle comprising multiple timeslots to manage shared resources and to schedule data ingress and egress through the ports of the current configuration, wherein each port is assigned one or more timeslots. The network switch may be reprogrammed to support one of multiple timeslot assignment schemes for one of multiple port configurations. The network switch may support configurations with varying numbers of ports, e. g. 8- and 16-port configurations. A network switch may also support configurations where two or more ports are combined to form one port, for example, a 2 Gbs Fibre Channel port. To meet the requirements of the various configurations, the timeslot assignment scheme may be reprogrammed to meet the scheduling requirements of each of the possible port configurations.