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Kaustuve Bhattacharyya

from Gilroy, CA
Age ~57

Kaustuve Bhattacharyya Phones & Addresses

  • 7963 Kipling Cir, Gilroy, CA 95020
  • 361 Nectar Ct, Gilroy, CA 95020 (408) 846-5342
  • Dallas, TX
  • 4215 Bostonian Dr, Schenectady, NY 12306 (518) 356-1051
  • Las Cruces, NM
  • Albany, NY
  • Santa Clara, CA
  • Hopewell Junction, NY

Work

Company: Asml Jun 2007 Position: Senior technical director

Education

Degree: Master of Science, Masters School / High School: New Mexico State University 1991 to 1994 Specialities: Chemical Engineering

Skills

Semiconductors • Product Management • Semiconductor Industry • Metrology • Engineering Management • R&D • Optics • Ic • Product Marketing • Technical Marketing • Design of Experiments • Thin Films • Silicon • Product Lifecycle Management • Software Development • Electronics • Simulations

Languages

English

Industries

Semiconductors

Resumes

Resumes

Kaustuve Bhattacharyya Photo 1

Senior Technical Director

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Location:
7963 Kipling Cir, Gilroy, CA 95020
Industry:
Semiconductors
Work:
Asml
Senior Technical Director

Kla-Tencor Feb 1998 - Jun 2007
Technical Marketing and Application Engineering Manager

Texas Instruments Sep 1995 - Feb 1998
Process Engineer
Education:
New Mexico State University 1991 - 1994
Master of Science, Masters, Chemical Engineering
Skills:
Semiconductors
Product Management
Semiconductor Industry
Metrology
Engineering Management
R&D
Optics
Ic
Product Marketing
Technical Marketing
Design of Experiments
Thin Films
Silicon
Product Lifecycle Management
Software Development
Electronics
Simulations
Languages:
English

Publications

Us Patents

Detailed Grey Scale Inspection Method And Apparatus

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US Patent:
7457454, Nov 25, 2008
Filed:
Oct 8, 2002
Appl. No.:
10/267016
Inventors:
Kaustuve Bhattacharyya - Schenectady NY, US
Assignee:
KLA-Tencor Technologies Corporation - Milpitas CA
International Classification:
G06K 9/00
G01R 31/26
G01L 21/30
US Classification:
382149, 438 6, 216 60
Abstract:
A method for inspecting semiconductor wafers and the like is presented. The method comprises initially determining a baseline greyscale difference, such as a greyscale plot or greyscale visual representation, for at least one baseline semiconductor wafer subjected to a process. The baseline greyscale difference represents a numerical difference between composite preprocessing and postprocessing greyscale representations of all pixels on the baseline semiconductor wafer. The method further comprises determining a preprocess greyscale representation for one wafer in the semiconductor wafer set and subjecting the one wafer in the semiconductor wafer set to the process, determining a postprocess greyscale representation of the one wafer in the semiconductor wafer set, and determining a difference for the one wafer in the semiconductor set. The difference represents any disparity between preprocess and postprocess greyscale representations of the one wafer in the semiconductor set. The method then compares the difference to the baseline greyscale difference.
Kaustuve Bhattacharyya from Gilroy, CA, age ~57 Get Report