Kathleen E Nickolls

20120089792, Apr 12, 2012

Sep 28, 2011

13/247855

Brian FAHS - Los Altos CA, US
John R. Nickolls - Los Altos CA, US
Kathleen Elliott Nickolls - Los Altos CA, US
Henry Packard Moreton - Woodside CA, US
Brett W. Coon - San Jose CA, US

G06F 12/00

711154, 711E12001

One embodiment of the present invention sets forth a technique providing an optimized way to allocate and access memory across a plurality of thread/data lanes. Specifically, the device driver receives an instruction targeted to a memory set up as an array of structures of arrays. The device driver computes an address within the memory using information about the number of thread/data lanes and parameters from the instruction itself. The result is a memory allocation and access approach where the device driver properly computes the target address in the memory. Advantageously, processing efficiency is improved where memory in a parallel processing subsystem is internally stored and accessed as an array of structures of arrays, proportional to the SIMT/SIMD group width (the number of threads or lanes per execution group).

20120110586, May 3, 2012

Sep 28, 2011

13/247819

Brett W. Coon - San Jose CA, US
John R. Nickolls - Los Altos CA, US
John Erik Lindholm - Saratoga CA, US
Robert J. Stoll - Los Altos CA, US
Nicholas Wang - Saratoga, CA
Jack Hilaire Choquette - Palo Alto CA, US
Kathleen Elliott Nickolls - Los Altos CA, US

G06F 9/46

718102

A parallel thread processor executes thread groups belonging to multiple cooperative thread arrays (CTAs). At each cycle of the parallel thread processor, an instruction scheduler selects a thread group to be issued for execution during a subsequent cycle. The instruction scheduler selects a thread group to issue for execution by (i) identifying a pool of available thread groups, (ii) identifying a CTA that has the greatest seniority value, and (iii) selecting the thread group that has the greatest credit value from within the CTA with the greatest seniority value.

20120084539, Apr 5, 2012

Sep 28, 2011

13/247833

Lars S. NYLAND - Carrboro NC, US
John R. Nickolls - Los Altos CA, US
Kathleen Elliott Nickolls - Los Altos CA, US

G06F 9/30

712229, 712E09016

Techniques are disclosed for executing conditional computer instructions in an efficient manner that reduces bubbles and idle states. In one embodiment, dual-function instruction execution is disclosed where the dual-function instruction has two possible functions (or operations), the choice of which is controlled by a predicate value with a true or false value. Among other things, the disclosed techniques provide dynamic control for choosing which operation to execute leading to more efficiently executed code.