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Kartik Nanda

from Austin, TX
Age ~48
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Also known as:
Nanda Nanda, Kartik Nanada, Nanda Kartik
Phone and address:
4600 Monterey Oaks Blvd, Austin, TX 78749
(512) 891-9293
Related to:
Aditi Nanda, 46Mrinal NandaAditi Nanda
Connected to:
Ashwini K Nanda, 62Bimal Nanda, 51Catherine A Nanda, 64Choudhury S Nanda, 41Gautam Nanda, 47Inderpreet Nanda, 40Jagdish L Nanda, 90Manju Nanda, 50Mitali Nanda, 42Munish F Nanda, 58

Kartik Nanda Phones & Addresses

  • 4600 Monterey Oaks Blvd, Austin, TX 78749 (512) 891-9293
  • 5104 Jekins Cv, Austin, TX 78730 (512) 342-8933
  • 3517 Hills Dr, Austin, TX 78731 (512) 372-9847
  • 1221 Congress Ave, Austin, TX 78704 (512) 916-8940
  • Framingham, MA
  • Wilmington, DE
  • 38 Middlesex St, Cambridge, MA 02140 (617) 945-2959
  • 9001 Markville Dr, Dallas, TX 75243 (214) 570-8034
  • 4600 Monterey Oaks Blvd, Austin, TX 78749 (512) 694-4552

Work

Position: Food Preparation and Serving Related Occupations

Resumes

Resumes

Kartik Nanda Photo 1

Fellow

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Location:
Austin, TX
Industry:
Computer Software
Work:
Analog Devices - Cambridge, MA since Jun 2011
Design Manager
Lyric Semiconductors (Acquired by ADI) - Cambridge, MA Jul 2010 - Jun 2011
ASIC Architect
Enphase Energy Mar 2009 - May 2010
ASIC Consultant
Cirrus Logic Nov 2001 - Nov 2008
Staff Engineer; Project Lead
Crystal Semiconductor (Cirrus Logic) Aug 1998 - Nov 2001
Design Engineer
Education:
University of Notre Dame 1996 - 1998
Indian Institute of Technology, Kanpur 1992 - 1996
Skills:
Mixed Signal
Ic
Analog
Asic
Semiconductors
Integrated Circuit Design
Algorithms
Digital Signal Processors
Embedded Systems
Verilog
Simulations
Application Specific Integrated Circuits
Integrated Circuits
R&D
Low Power Design
Fpga
C
Machine Learning
System Architecture
System on A Chip
Engineering
Electronics
Product Development
Product Management
Project Management
Cross Functional Team Leadership
Matlab
C++
Electrical Engineering
Solar
Renewable Energy Systems
Python
Strategy
Artificial Intelligence
Bayesian Inference
Digital Signal Processing
Certifications:
Applied Machine Learning In Python
Introduction To Data Science In Python
Applied Plotting, Charting & Data Representation In Python
Kartik Nanda Photo 2

Kartik Nanda

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Kartik Nanda Photo 3

Kartik Nanda

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Kartik Nanda
Managing M, Managing
CLEANTECH INTEGRATED CIRCUITS LLC
Mfg Electronic Components
5104 Jekins Cv, Austin, TX 78730
6606 Mapleshade Ln, Dallas, TX 75252

Publications

Us Patents

Techniques For Spreading Zeros In A Digital Filter With Minimal Use Of Registers

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US Patent:
6871207, Mar 22, 2005
Filed:
Dec 20, 1999
Appl. No.:
09/466835
Inventors:
Kartik Nanda - Nashua NH, US
Dan Kasha - Providence RI, US
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
G06F017/17
US Classification:
708313
Abstract:
Techniques related to a digital filter include at least one decimator disposed between an integrator section and a comb section such that the transfer function of the filter has split zeros. The resulting filter implementation employs considerable less silicon real estate than other prior art implementations with spread zeros, and has more design flexibility with improved resulting performance than the Hogenauer implementation.

Circuits And Methods For Exchanging Data Through A Serial Port And Systems Using The Same

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US Patent:
7145486, Dec 5, 2006
Filed:
Mar 24, 2005
Appl. No.:
11/089112
Inventors:
Amiya Anand Chokhawala - Austin TX, US
Kartik Nanda - Austin TX, US
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H03M 9/00
US Classification:
341100, 341 50, 710 30
Abstract:
A method of exchanging data through a serial port includes transmitting data as an output stream of frames defined by edges of a frame clock signal, a first data bit of a current frame transmitted during a time period starting in a preceding frame and extending after an edge of the frame clock signal defining the start of the current frame.

Scheme For Determining Internal Mode Using Mclk Frequency Autodetect

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US Patent:
7193549, Mar 20, 2007
Filed:
Jul 15, 2004
Appl. No.:
10/891944
Inventors:
Kartik Nanda - Austin TX, US
Giri Rangan - Austin TX, US
Aryesh Amar - Austin TX, US
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H03M 1/66
US Classification:
341144, 341123, 341 61
Abstract:
A method of determining an internal operating mode of an electronic circuit derives multiple comparison rates from a rate of a master clock input, computes one or more clock ratios of the comparison rates to a rate of a sample rate clock input, and determines whether any of the clock ratios is a valid ratio representing a supported clock configuration. The appropriate internal operating mode is then selected based on the valid ratio. In the illustrative embodiment, a clock autodetect unit uses two trip frequencies to derive at least first and second clock comparison rates. The audio converter can operate in three distinct modes (base, high and quad modes). The base mode is selected when the clock ratio is about 256, the high mode is selected when the clock ratio is about 128, and the quad mode is selected when the clock ratio is about 64. A multiplexer can be used to sequence through the computer clock ratios to ensure that a highest valid ratio is used among a plurality of valid ratios.

Systems And Methods For Clock Mode Determination Utilizing Divide Ratio Testing

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US Patent:
7286069, Oct 23, 2007
Filed:
May 24, 2005
Appl. No.:
11/136215
Inventors:
Bruce Eliot Duewer - Austin TX, US
John Laurence Melanson - Austin TX, US
Kartik Nanda - Austin TX, US
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H03M 1/00
US Classification:
341123, 341122
Abstract:
A system for determining a data converter operating mode includes measurement circuitry for measuring master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency and a mapping system for mapping the measurement of the frequency ratio to an operating mode of the data converter. The mapping system generates a set of candidate divide ratios for dividing the master clock frequency to generate corresponding internal master clock frequencies of an internal clock signal and determines the lowest divide ratio which generates a supported internal master clock frequency. In an alternate embodiment, the mapping system determines the divide ratio required by a filter of the data converter by dividing the data clock to master clock frequency ratio by a data clock to internal clock frequency ratio between the data clock frequency and the frequency of an internal clock signal. In additional embodiments, the mapping system gives preference to natural number divide ratios during mode mapping.

Delta-Sigma Modulator Having Quantizer Code Pattern Detection Controlled Dither

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US Patent:
7317411, Jan 8, 2008
Filed:
Sep 21, 2006
Appl. No.:
11/534195
Inventors:
Kartik Nanda - Austin TX, US
Timothy Thomas Rueger - Austin TX, US
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H03M 3/00
US Classification:
341143, 341131
Abstract:
A delta-sigma having quantizer code pattern detection controlled dither reduces the probability of “stuck” code sequences that occur when the input signal and feedback signal are equal and thus no quantizer output change occurs. In particular, in modulators that are periodically reset, the pattern detection and dither control reduce the probability of a stuck code sequence at startup. A pattern detection circuit detects a sequence of unchanging quantizer output values and injects a signal at the quantizer input to cause the quantizer to change levels. The injected signal may be a dither signal that is increased in amplitude in response to the detection of unchanging code sequences and then decreased when the quantizer output changes.

Circuits And Methods For Reducing The Effects Of Level Shifter Delays In Systems Operating In Multiple Voltage Domains

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US Patent:
7348813, Mar 25, 2008
Filed:
Dec 2, 2005
Appl. No.:
11/292523
Inventors:
Kartik Nanda - Austin TX, US
Aryesh Amar - Austin TX, US
Rahul Singh - Austin TX, US
Jerome E Johnston - Austin TX, US
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H03L 7/00
US Classification:
327141, 327333
Abstract:
A method of interfacing circuits operating in different voltage domains includes receiving a first signal with a first circuit operating in a first voltage domain and generating a second signal with a second circuit operating in a second voltage domain. The second signal is level shifted between the first and second voltage domains with a level shifter and synchronized with the first signal with a third circuit operating in the first voltage domain.

Systems And Methods For Clock Mode Determination Utilizing Prioritization Criteria

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US Patent:
7352303, Apr 1, 2008
Filed:
May 24, 2005
Appl. No.:
11/135995
Inventors:
Bruce Eliot Duewer - Austin TX, US
John Laurence Melanson - Austin TX, US
Kartik Nanda - Austin TX, US
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H03M 7/00
US Classification:
341 61, 341123
Abstract:
A system for determining a data converter operating mode includes measurement circuitry that measures a master clock frequency of a master clock signal received without a modification in frequency from a master clock signal source and that measures a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In other embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter based on mode priority constraints. In additional embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter by narrowing the choices of master clock divide ratios and subsequently determining an operating mode from the frequency ratio.

Delta-Sigma Analog-To-Digital Converter (Adc) Having An Intermittent Power-Down State Between Conversion Cycles

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US Patent:
7365667, Apr 29, 2008
Filed:
Sep 21, 2006
Appl. No.:
11/534191
Inventors:
Kartik Nanda - Austin TX, US
John L. Melanson - Austin TX, US
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H03M 3/00
US Classification:
341143, 341155
Abstract:
A delta-sigma analog to digital converter (ADC) having an intermittent power down state between conversion cycles provides for power consumption savings when the converter is in a lower sample rate operating mode. Clocks provided to the digital portions of the converter are disabled, except for a periodic interval in which a conversion is performed at the higher selectable sample rate of the converter. The analog portions of the converter can also be disabled, but are re-enabled for a predetermined time period and reset before the digital clocks are enabled, so that the loop filter and feedback value supplied from the quantizer to the loop filter are stable prior to each conversion.
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Kartik Nanda from Austin, TX, age ~48 Get Report