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Karen D Darbinyan

from Pleasanton, CA
Age ~62
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Also known as:
Karen D Ruzanna
Phone and address:
5536 Corte Sierra, Pleasanton, CA 94566
(925) 485-3697
Related to:
Hakob DarbinyanTigran Darbinyan, 34Ruzanna KyurkchyanRuzanna Darbinyan
Connected to:
Vahan Darbinyan, 40Vardan B Darbinyan, 61Cambria L Darbison, 50Heather E Darbo, 51Lamin Darboe, 58Yusupha K Darboe, 54Ann Darbonne, 64Christopher Darbonne, 61Dawn R Darbonne, 56Erica D Darbonne, 39

Karen Darbinyan Phones & Addresses

  • 5536 Corte Sierra, Pleasanton, CA 94566 (925) 485-3697
  • Fremont, CA
  • Alameda, CA
  • 5536 Corte Sierra, Pleasanton, CA 94566

Publications

Us Patents

Method And Apparatus For A Command Based Bist For Testing Memories

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US Patent:
7290186, Oct 30, 2007
Filed:
Sep 16, 2003
Appl. No.:
10/664190
Inventors:
Yervant Zorian - Santa Clara CA, US
Gevorg Torjyan - Yerevan, AM
Karen Darbinyan - Fremont CA, US
Albert Harutyunyan - Yerevan, AM
Assignee:
Virage Logic Corporation - Fremont CA
International Classification:
G11C 29/00
G01R 31/28
US Classification:
714718, 714733
Abstract:
Methods and apparatuses in which two or more memories share a processor for Built In Self Test algorithms and features are described. The processor initiates a Built In Self Test for the memories. Each memory has an intelligence wrapper bounding that memory. Each intelligence wrapper contains control logic to decode a command from the processor. Each intelligence wrapper contains logic to execute a set of test vectors on a bounded memory. The processor sends a command based self-test to each intelligence wrapper at a first clock speed and the control logic executes the operations associated with that command at a second clock speed asynchronous with the first speed. The processor loads the command containing representations of a march element and data to one or more of the intelligence wrappers via a serial bus.

Methods And Apparatuses That Reduce The Size Of A Repair Data Container For Repairable Memories

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US Patent:
7415640, Aug 19, 2008
Filed:
Oct 13, 2003
Appl. No.:
10/684793
Inventors:
Yervant Zorian - Santa Clara CA, US
Gevorg Torjyan - Yerevan, AM
Karen Darbinyan - Fremont CA, US
Assignee:
Virage Logic Corporation - Fremont CA
International Classification:
G11C 29/00
US Classification:
714711, 714718, 714723, 365200, 365201
Abstract:
Various methods and apparatuses are described in which a repair data container may store a concatenated repair signature for multiple memories having one or more redundant components associated with each memory. A processor contains redundancy allocation logic to execute one or more repair algorithms to generate a repair signature for each memory. The repair data container may store actual repair signatures for each memory having one or more defective memory cells detected during fault testing and dummy repair signatures for each memory with no defective memory cells. The processor may contain logic configured to compress an amount of bits making up the concatenated repair signature, to decompress the amount of bits making up the concatenated repair signature, and to compose the concatenated repair signature for all of the memories sharing the repair data container. The repair data container may have an amount of fuses to store the actual repair signatures for an adjustable subset of the multiple memories.

System And Method For Verifying Ip Integrity In System-On-Chip (Soc) Design

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US Patent:
7673264, Mar 2, 2010
Filed:
Apr 5, 2007
Appl. No.:
11/732900
Inventors:
Karen Darbinyan - Fremont CA, US
Hayk Chukhajyan - Yerevan, AM
Albert Harutyunyan - Yerevan, AM
Yervant Zorian - Santa Clara CA, US
Assignee:
Virage Logic Corp. - Fremont CA
International Classification:
G06F 17/50
US Classification:
716 5, 716 7, 716 16
Abstract:
An intellectual property (IP) integrity verification system and method operable with respect to integrating an IP design into a user's embedded IC design. In one embodiment, the IP design is partitioned into a plurality of IP modules based on the requirements of the embedded IC design. For each IP module, a corresponding integrity checker module is provided, wherein each integrity checker module has a port-wise correspondence with its corresponding IP module. The embedded IC design is simulated with the integrity checker modules rather than the IP modules for generating a netlist, which may be verified with respect to any interconnectivity errors associated with the IP modules.

Architecture, System And Method For Compressing Repair Data In An Integrated Circuit (Ic) Design

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US Patent:
7898882, Mar 1, 2011
Filed:
Jun 22, 2007
Appl. No.:
11/766943
Inventors:
Karen Darbinyan - Fremont CA, US
Gevorg Torjyan - Fremont CA, US
Yervant Zorian - Santa Clara CA, US
Mher Mkhoyan - Yerevan, AM
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G11C 29/44
G06F 11/20
US Classification:
365200, 365201, 3652257, 36523003, 36518509, 36518511, 714 42
Abstract:
Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored in a shared nonvolatile storage common to the memory instances.

Architecture, System And Method For Compressing Repair Data In An Integrated Circuit (Ic) Design

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US Patent:
8295108, Oct 23, 2012
Filed:
Jan 21, 2011
Appl. No.:
13/011696
Inventors:
Karen Darbinyan - Fremont CA, US
Gevorg Torjyan - Fremont CA, US
Yervant Zorian - Santa Clara CA, US
Mher Mkhoyan - Yerevan, AM
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G11C 29/44
G06F 11/20
US Classification:
365200, 365201, 3652257, 36523003, 36518509, 36518511, 714 42, 714718
Abstract:
Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored in a shared nonvolatile storage common to the memory instances.

Memory Hard Macro Partition Optimization For Testing Embedded Memories

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US Patent:
20130080847, Mar 28, 2013
Filed:
Sep 23, 2011
Appl. No.:
13/243897
Inventors:
Yervant Zorian - Santa Clara CA, US
Karen Darbinyan - Pleasanton CA, US
Gevorg Torjyan - Fremont CA, US
Assignee:
SYNOPSYS, INC. - Mountain View CA
International Classification:
G11C 29/12
G06F 11/27
US Classification:
714718, 714E11169
Abstract:
A memory hard macro designed to support multiple design for test (DFT) techniques having signal paths associated with the DFT techniques and the functional operation of the memory instance that share logic devices or components. The memory hard macro includes a functional input port and a functional output port, forming a functional memory data path, which includes input latches from the memory instance. The memory hard macro also includes a scan input port and a scan output port, forming a scan data path, which includes input latches from the array of data buffer circuits and output latches from the array of sense amplifiers. The memory hard macro further includes a BIST input port and a BIST output port, forming a BIST data path, which includes at least one input latch from the array of data buffer circuits and at least one output latch from the array of sense amplifiers.

Generation Of Memory Structural Model Based On Memory Layout

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US Patent:
20130346056, Dec 26, 2013
Filed:
Jun 22, 2012
Appl. No.:
13/531189
Inventors:
Karen Amirkhanyan - Yerevan, AM
Karen Darbinyan - Pleasanton CA, US
Arman Davtyan - Yerevan, AM
Gurgen Harutyunyan - Abovyan, AM
Samvel Shoukourian - Yerevan, AM
Valery Vardanian - Yerevan, AM
Yervant Zorian - Santa Clara CA, US
Assignee:
SYNOPSYS, INC. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
703 14
Abstract:
A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine.

Apparatus, Method, And System Having A Pin To Activate The Self-Test And Repair Instructions

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US Patent:
7149924, Dec 12, 2006
Filed:
Sep 5, 2002
Appl. No.:
10/236248
Inventors:
Yervant Zorian - Santa Clara CA, US
Gevorg Toriyan - Yerevan, AM
Karen Darbinyan - Fremont CA, US
Assignee:
Virage Logic Corporation - Fremont CA
International Classification:
G06F 11/00
US Classification:
714 30, 714718
Abstract:
In general, various methods, apparatuses, and systems in which a processor that contains self test and repair instructions to be executed on a memory is coupled to a first external pin. Assertion of a signal on the first external pin activates execution of the self-test and repair instructions on the memory.
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Karen D Darbinyan from Pleasanton, CA, age ~62 Get Report