Kalpana R Ramakrishnan

6732260, May 4, 2004

Mar 6, 2000

09/518939

Hong Wang - Fremont CA
Ralph Kling - Sunnyvale CA
Edward T. Grochowski - San Jose CA
Kalpana Ramakrishnan - Belmont CA

Intel Corporation - Santa Clara CA

G06F 1500

712237, 712207

An instruction prefetch apparatus includes a branch target buffer (BTB), a presbyopic target buffer (PTB) and a prefetch stream buffer (PSB). The BTB includes records that map branch addresses to branch target addresses, and the PTB includes records that map branch target addresses to subsequent branch target addresses. When a branch instruction is encountered, the BTB can predict the dynamically adjacent subsequent block entry location as the branch target address in the record that also includes the branch instruction address. The PTB can predict multiple subsequent blocks by mapping the branch target address to subsequent dynamic blocks. The PSB holds instructions prefetched from subsequent blocks predicted by the PTB.

7516312, Apr 7, 2009

Apr 2, 2004

10/817263

Hong Wang - Fremont CA, US
Ralph Kling - Sunnyvale CA, US
Edward T. Grochowski - San Jose CA, US
Kalpana Ramakrishnan - Belmont CA, US

Intel Corporation - Santa Clara CA

G06F 15/00
G06F 9/00

712237, 712207

An instruction prefetch apparatus includes a branch target buffer (BTB), a presbyopic target buffer (PTB) and a prefetch stream buffer (PSB). The BTB includes records that map branch addresses to branch target addresses, and the PTB includes records that map branch target addresses to subsequent branch target addresses. When a branch instruction is encountered, the BTB can predict the dynamically adjacent subsequent block entry location as the branch target address in the record that also includes the branch instruction address. The PTB can predict multiple subsequent blocks by mapping the branch target address to subsequent dynamic blocks. The PSB holds instructions prefetched from subsequent blocks predicted by the PTB.

60121343, Jan 4, 2000

Apr 9, 1998

9/057968

Rory McInerney - Sunnyvale CA
Eric Sindelar - Sunnyvale CA
Tse-Yu Yeh - Milpitas CA
Kalpana Ramakrishnan - Belmont CA

Institute for the Development of Emerging Architectures, L.L.C. - Cupertino CA

G06F 934
G06F 938

711207

A computer processor with a mechanism for improved prefetching of instrucns into a local cache includes an instruction pointer multiplexer that generates one of a plurality of instruction pointers in a first pipeline stage, which is used to produce a physical address from an ITLB lookup. A comparison is performed by compare logic between the physical address (and tags) of a set in the local cache and the set associated with the selected instruction pointer. A way multiplexer selects the proper way output from either the compare logic or an instruction streaming buffer that stores instructions returned from the first cache, but not yet written into the local cache. An instruction is bypassed to the way multiplexer from the instruction streaming buffer in response to an instruction streaming buffer hit and a miss signal by the compare logic.