Resumes
Resumes

Kai Chang
View pageWork:
Intel Corp
Feb 2014 to 2000
Senior Fault Isolation and Debug Engineer
Intel Corp
Santa Clara, CA
Jun 2008 to Jan 2014
Senior Logic Design and Debug Engineer
Intel Corp
Santa Clara, CA
Jan 2006 to May 2008
Component Design and Debug Engineer
Hewlett Packard/Intel Corp
Fort Collins, CO
May 2001 to Dec 2005
Circuit Design Engineer
Feb 2014 to 2000
Senior Fault Isolation and Debug Engineer
Intel Corp
Santa Clara, CA
Jun 2008 to Jan 2014
Senior Logic Design and Debug Engineer
Intel Corp
Santa Clara, CA
Jan 2006 to May 2008
Component Design and Debug Engineer
Hewlett Packard/Intel Corp
Fort Collins, CO
May 2001 to Dec 2005
Circuit Design Engineer
Education:
Columbia University
New York, NY
May 2001
M.S. in Electrical Engineering
National Sun Yat-Sen University
1992 to 1996
B.S. in Electrical Engineering
New York, NY
May 2001
M.S. in Electrical Engineering
National Sun Yat-Sen University
1992 to 1996
B.S. in Electrical Engineering
Skills:
Computer languages: System Verilog, VCS, C/C++, Perl, Python Operating systems: UNIX, Linux, Microsoft Windows CAD tools: Cadence Virtuoso Schematics & Layout Editor, Synopsys DC, HSpice