Kai Chieh Chan

6677793, Jan 13, 2004

Feb 3, 2003

10/357827

Kai Keung Chan - Fremont CA
Jung-Sheng Hoei - Newark CA
Pankaj Joshi - Milpitas CA
Leo Fang - Belmont CA

LSI Logic Corporation - Milpitas CA

H03L 706

327158, 327291

An automatic delay matching circuit for a data serializer includes a phase-locked loop for synthesizing a transmitter clock signal for an external circuit, a phase interpolator coupled to the phase-locked loop for delaying or advancing the transmitter clock signal in response to a phase control signal to generate a delayed or advanced transmitter clock signal for the data serializer, a phase detector for measuring a phase difference between the delayed or advanced transmitter clock signal further delayed through the data serializer and the transmitter clock signal delayed through an external circuit, and a loop filter coupled to the phase detector for generating the phase control signal as a function of the phase difference between the delayed or advanced transmitter clock signal further delayed through the data serializer and the transmitter clock signal delayed through the external circuit.

7869547, Jan 11, 2011

Apr 4, 2007

11/784195

Haitao Xia - Santa Clara CA, US
Shih-Ming Shih - San Jose CA, US
Ryan Yu - Sunnyvale CA, US
Marcus Marrow - Santa Clara CA, US
Kai Keung Chan - Fremont CA, US

Link—A—Media Devices Corporation - Santa Clara CA

H04L 27/06

375344, 375339

Timing acquisition is performed. A first portion of a preamble having an end is sampled. A first phase value is determined based on the sampled first portion. A second portion of the preamble is sampled and a second phase value is determined based on the sampled second portion. An end phase value is extrapolated based at least in part the first phase value and the second phase value. A clock is adjusted using the extrapolated end phase value.

7974033, Jul 5, 2011

Apr 13, 2007

11/787230

Kwok W. Yeung - Milpitas CA, US
Kai Keung Chan - Fremont CA, US
Paul K. Lai - San Jose CA, US

Link—A—Media Devices Corporation - Santa Clara CA

G11B 5/09
G11B 5/02

360 50, 360 48, 360 55

Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is accessed by the read channel.

8077814, Dec 13, 2011

Dec 3, 2010

12/960043

Haitao Xia - Santa Clara CA, US
Shih-Ming Shih - San Jose CA, US
Ryan Yu - Sunnyvale CA, US
Marcus Marrow - Santa Clara CA, US
Kai Keung Chan - Fremont CA, US

Link—A—Media Devices Corporation - Santa Clara CA

H04L 27/06

375344, 375339

A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop.

8320512, Nov 27, 2012

Nov 7, 2011

13/291024

Haitao Xia - Santa Clara CA, US
Shih-Ming Shih - San Jose CA, US
Ryan Yu - Sunnyvale CA, US
Marcus Marrow - Santa Clara CA, US
Kai Keung Chan - Fremont CA, US

Link—A—Media Devices Corporation - Santa Clara CA

H04L 7/00

375371, 375354

A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop.

8489971, Jul 16, 2013

May 27, 2011

13/117955

Kai Keung Chan - Fremont CA, US
Kin Man Ng - Cupertino CA, US
Jason Bellorado - Santa Clara CA, US

SK hynix memory solutions inc. - San Jose CA

H03M 13/03

714795

A system for adapting coefficients of a soft output Viterbi algorithm (SOVA) is disclosed. The system includes a receiver configured to select an output of an SOVA detector at least in part based on a criterion. The receiver is configured to store the selected output of the SOVA detector. The receiver is further configured to store a signal that corresponds to the stored selected output of the SOVA detector, wherein the input to the SOVA detector is derived from the signal. The receiver is further configured to adapt a plurality of coefficients of the SOVA detector at least in part based on the stored selected output of the SOVA detector, the stored signal, and a corresponding data pattern. The system includes an interface coupled to the receiver and configured to receive samples.

8570680, Oct 29, 2013

May 23, 2011

13/113926

Kwok W. Yeung - Milpitas CA, US
Kai Keung Chan - Fremont CA, US
Paul K. Lai - San Jose CA, US

SK hynix memory solutions inc. - San Jose CA

G11B 5/09
G11B 5/02

360 50, 360 48, 360 55

Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is accessed by the read channel.

8631311, Jan 14, 2014

Apr 23, 2012

13/453729

Kai Keung Chan - Fremont CA, US
Yu Kou - San Jose CA, US
Wing Hui - San Jose CA, US

SK hynix memory solutions inc. - San Jose CA

G06F 11/00

714799, 714769

A method for recovering data is disclosed. A sensed analog signal is converted into digital samples using an analog-to-digital converter (ADC). The digital samples are processed into processed digital samples using a first filter. The processed digital samples are decoded into decoded data. Whether the decoded data is acceptable is then determined. The processed digital samples are fed back to the first filter using a reprocessing circuit such that the processed digital samples are reprocessed into reprocessed digital samples in the event that the decoded data is unacceptable. A set of reprocessing coefficients is provided for the first filter to reprocess the processed digital samples.