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Justin B Dorhout

from Boise, ID
Age ~43
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Also known as:
Justin Bradley Dorhout
Related to:
Wouter G Vanlaren, 53Stacia L Vanderstoep, 33
Connected to:
Arnold G Dorhout, 85Jennifer K Dorhout, 36Marlin J Dorhout, 81Sean A Dorhout, 42Allen M Dori, 56Barbara A Dori, 81Tal Dori, 56Tia S Dori, 60Aaron J Doria, 30Abelardo S Doria, 59

Justin Dorhout Phones & Addresses

  • Boise, ID
  • Minneapolis, MN
  • 4856 380Th St, Hospers, IA 51238 (712) 324-2760
  • Ames, IA

Work

Company: Micron technology Aug 2012 Address: Boise, Idaho Area Position: Nand process integration engineer

Education

Degree: Master of Science (MS) School / High School: Iowa State University 2004 to 2006 Specialities: Electrical and Electronics Engineering

Skills

Thin Films

Industries

Semiconductors

Resumes

Resumes

Justin Dorhout Photo 1

Senior Manager - Nand Process Integration

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Location:
Boise, ID
Industry:
Semiconductors
Work:
Micron Technology - Boise, Idaho Area since Aug 2012
NAND Process Integration Engineer
Micron Technology Jun 2006 - Aug 2012
Photolithography Development Engineer
Iowa State University 2004 - 2006
Research Assistant
Education:
Iowa State University 2004 - 2006
Master of Science (MS), Electrical and Electronics Engineering Dordt College 1999 - 2003
BSEE, Electrical Engineering
Skills:
Thin Films

Publications

Us Patents

Methods Of Forming Semiconductor Constructions

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US Patent:
20130341795, Dec 26, 2013
Filed:
Jun 21, 2012
Appl. No.:
13/529006
Inventors:
Justin B. Dorhout - Boise ID, US
Ranjan Khurana - Boise ID, US
David Swindler - Boise ID, US
Jianming Zhou - Boise ID, US
Assignee:
MICRON TECHNOLOGY, INC. - Boise ID
International Classification:
H01L 21/311
H01L 21/768
H01L 23/48
US Classification:
257773, 438702, 438669, 257E23011, 257E2159, 257E21257
Abstract:
Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.

Microelectronic Devices Including Support Pillar Structures, And Related Memory Devices

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US Patent:
20220367500, Nov 17, 2022
Filed:
Jul 29, 2022
Appl. No.:
17/816299
Inventors:
- Boise ID, US
Indra V. Chary - Boise ID, US
Justin B. Dorhout - Boise ID, US
International Classification:
H01L 27/11556
H01L 23/00
G11C 5/02
H01L 23/538
H01L 21/768
H01L 27/11582
G11C 5/06
Abstract:
A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulative structures, first support pillar structures extending through the stack structure within a first region of the microelectronic device, the first support pillar structures electrically isolated from a source structure underlying the stack structure, second support pillar structures extending through the stack structure within a second region of the microelectronic device, the second support pillar structures comprising an electrically conductive material in electrical communication with the source structure, and bridge structures extending between at least some neighboring first support pillar structures of the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

Methods Of Forming Microelectronic Devices, And Related Memory Devices, And Electronic Systems

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US Patent:
20220181352, Jun 9, 2022
Filed:
Feb 24, 2022
Appl. No.:
17/652425
Inventors:
- Boise ID, US
Indra V. Chary - Boise ID, US
Justin B. Dorhout - Boise ID, US
International Classification:
H01L 27/11582
H01L 27/11519
H01L 27/11524
G11C 16/08
H01L 27/11565
H01L 27/1157
H01L 27/11556
Abstract:
A method of forming a microelectronic device comprises forming a microelectronic device structure. The microelectronic device structure comprises a stack structure comprising insulative structures and additional insulative structures vertically alternating with the insulative structures, a dielectric structure vertically extending partially through the stack structure, and a dielectric material vertically overlying and horizontally extending across the stack structure and the dielectric structure. Portions of at least the dielectric material and the dielectric structure are removed to form a trench vertically overlying and at least partially horizontally overlapping a remaining portion of the dielectric structure. The trench is substantially filled with additional dielectric material. Microelectronic devices, memory devices, and electronic systems are also described.

Methods Of Forming Electronic Devices With Channel Openings Or Pillars Extending Through A Tier Stack

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US Patent:
20230092501, Mar 23, 2023
Filed:
Nov 7, 2022
Appl. No.:
18/053134
Inventors:
- Boise ID, US
Nancy M. Lomeli - Boise ID, US
Justin B. Dorhout - Boise ID, US
Damir Fazil - Boise ID, US
International Classification:
H01L 27/11582
H01L 27/11524
H01L 27/11573
H01L 27/11529
H01L 27/1157
H01L 27/11556
Abstract:
Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.

Microelectronic Devices Including Stair Step Structures, And Related Electronic Systems And Methods

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US Patent:
20230063178, Mar 2, 2023
Filed:
Dec 29, 2021
Appl. No.:
17/564633
Inventors:
- Boise ID, US
Matthew J. King - Boise ID, US
Jason Reece - Boise ID, US
Michael J. Gossman - Meridian ID, US
Shruthi Kumara Vadivel - Boise ID, US
Martin J. Barclay - Middleton ID, US
Lifang Xu - Boise ID, US
Joel D. Peterson - Boise ID, US
Matthew Park - Boise ID, US
Adam L. Olson - Boise ID, US
David A. Kewley - Boise ID, US
Xiaosong Zhang - Boise ID, US
Justin B. Dorhout - Boise ID, US
Zhen Feng Yow - Singapore, SG
Kah Sing Chooi - Singapore, SG
Tien Minh Quan Tran - Singapore, SG
Biow Hiem Ong - Singapore, SG
International Classification:
H01L 23/528
H01L 23/522
H01L 21/768
Abstract:
A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.

Microelectronic Devices Including Stair Step Structures, And Related Memory Devices, Electronic Systems, And Methods

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US Patent:
20210398997, Dec 23, 2021
Filed:
Jun 22, 2020
Appl. No.:
16/908287
Inventors:
- Boise ID, US
Indra V. Chary - Boise ID, US
Justin B. Dorhout - Boise ID, US
International Classification:
H01L 27/11556
H01L 23/00
G11C 5/02
G11C 5/06
H01L 21/768
H01L 27/11582
H01L 23/538
Abstract:
A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulative structures, first support pillar structures extending through the stack structure within a first region of the microelectronic device, the first support pillar structures electrically isolated from a source structure underlying the stack structure, second support pillar structures extending through the stack structure within a second region of the microelectronic device, the second support pillar structures comprising an electrically conductive material in electrical communication with the source structure, and bridge structures extending between at least some neighboring first support pillar structures of the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

Integrated Assemblies Having Conductive Posts Extending Through Stacks Of Alternating Materials

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US Patent:
20210375894, Dec 2, 2021
Filed:
Aug 6, 2021
Appl. No.:
17/395751
Inventors:
- Boise ID, US
Indra V. Chary - Boise ID, US
Justin B. Dorhout - Boise ID, US
Rita J. Klein - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27/11529
G11C 5/06
H01L 27/11524
H01L 27/11582
H01L 27/1157
H01L 27/11573
H01L 27/11556
Abstract:
Some embodiments include an integrated assembly having a conductive expanse over conductive nodes. The conductive nodes include a first composition. A bottom surface of the conductive expanse includes a second composition which is different composition than the first composition. A stack is over the conductive expanse. The stack includes alternating first and second levels. Pillar structures extend vertically through the stack. Each of the pillar structures includes a post of conductive material laterally surrounded by an insulative liner. At least one of the posts extends through the conductive expanse to directly contact one of the conductive nodes. Some embodiments include methods of forming integrated assemblies.

Integrated Assemblies Which Include Stacked Memory Decks, And Methods Of Forming Integrated Assemblies

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US Patent:
20210358951, Nov 18, 2021
Filed:
Aug 2, 2021
Appl. No.:
17/391453
Inventors:
- Boise ID, US
Justin B. Dorhout - Boise ID, US
Nirup Bandaru - Boise ID, US
Damir Fazil - Boise ID, US
Nancy M. Lomeli - Boise ID, US
Purnima Narayanan - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27/11582
H01L 27/11524
H01L 27/1157
H01L 27/11556
H01L 27/11565
H01L 27/11519
Abstract:
Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.
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Justin B Dorhout from Boise, ID, age ~43 Get Report