Search

Julio Arceo

from San Diego, CA
Age ~54
Get Report
Related to:
Jorge Gonzalez, 56Santiago R Ramos, 64Jose ViramontesJesse Viramontes, 53Veronica Lazaro, 56Alicia Lazaro, 60Leopoldo Lazaro, 62Monica Lazaro, 50Teresa V ArceoRosalia G Arceo, 78Cipriano LazaroGalvez Lazaro Cipriano, 68Martin O Viramontes, 57Guadalupe Lazaro, 70Miguel S Arceo, 36Santiago G Arceo, 82Carmen Lazaro, 71
Connected to:
Aaron Arceo, 29Adrian Arceo, 32Agustin A Arceo, 69Alberto Arceo, 72Arlene B Arceo, 29Austin A Arceo, 39Benjamin Arceo, 75Cristian Arceo, 32Denise Arceo, 35Dennis Arceo, 36

Julio Arceo Phones & Addresses

  • 10271 Lone Dove St, San Diego, CA 92127 (858) 487-0944
  • 16504 Gettysburg Dr, San Diego, CA 92127
  • Imperial, CA
  • 3134 Via Alicante, La Jolla, CA 92037
  • 3927 Miramar St, La Jolla, CA 92037

Resumes

Resumes

Julio Arceo Photo 1

Senior Staff Engineer

View page
Location:
San Diego, CA
Industry:
Wireless
Work:
Qualcomm
Senior Staff Engineer

Publications

Us Patents

Direct Memory Swapping Between Nand Flash And Sram With Error Correction Coding

View page
US Patent:
20030156454, Aug 21, 2003
Filed:
Feb 21, 2002
Appl. No.:
10/081503
Inventors:
Jian Wei - San Diego CA, US
Inyup Kang - San Diego CA, US
Julio Arceo - San Diego CA, US
Jalal Husseini - San Diego CA, US
Tao Li - San Diego CA, US
Bruce Meagher - San Diego CA, US
Richard Higgins - San Diego CA, US
Moto Oishi - San Diego CA, US
Brian Rodrigues - San Diego CA, US
International Classification:
G11C016/04
US Classification:
365/185170, 365/154000
Abstract:
Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage units, and a data bus coupled to both storage units and the EMI unit. The two storage units are implemented external to the ASIC, and each storage unit is operable to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.

Non-Ported Generic Device (Software Managed Generic Device)

View page
US Patent:
20120278518, Nov 1, 2012
Filed:
Oct 25, 2011
Appl. No.:
13/281329
Inventors:
Hans Georg Gruber - San Diego CA, US
Julio Arceo - San Diego CA, US
Magesh Hariharan - San Diego CA, US
Suren Mohan - San Diego CA, US
Mark A. Landguth - La Jolla CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 13/00
US Classification:
710104
Abstract:
Techniques are disclosed for utilizing a non-ported generic device (NGD) or other non-ported hardware to couple processing device(s) to access components on a serial data bus without the need for integrated manager hardware. Using the NGD, a processing device(s) can utilize available unused bandwidth on the serial data bus to communicate with components coupled with the serial data bus, including a processing device having the manager hardware. Various alterations and embodiments are disclosed.

Waking A Media Bus

View page
US Patent:
20120278646, Nov 1, 2012
Filed:
Mar 21, 2012
Appl. No.:
13/426374
Inventors:
Hans Georg GRUBER - San Diego CA, US
Julio ARCEO - San Diego CA, US
Magesh HARIHARAN - San Diego CA, US
Suren MOHAN - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
G06F 1/12
US Classification:
713400
Abstract:
Arrangements for restarting data transmission on a serial low-power inter-chip media bus (SLIMbus) are presented. A clock signal may be provided in an active mode to a component communicatively coupled with the SLIMbus. Immediately prior to the clock signal in the active mode being provided, the clock signal may have been in a paused mode. While the clock signal was in the paused mode at least until the clock signal is provided in the active mode, the data line may have been inactive (e.g., a toggle on the data line may not have been present). Frame synchronization data for a frame may be transmitted. The frame synchronization data for the frame, as received by the component, may not match expected frame synchronization data. Payload data may be transmitted as part of the frame to the component, wherein the payload data is expected to be read properly by the component.

Multiple Slimbus Controllers For Slimbus Components

View page
US Patent:
20130019038, Jan 17, 2013
Filed:
Jan 17, 2012
Appl. No.:
13/352163
Inventors:
Hans Georg Gruber - San Diego CA, US
Julio Arceo - San Diego CA, US
Magesh Hariharan - San Diego CA, US
Suren Mohan - San Diego CA, US
Mark A. Landguth - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 13/14
US Classification:
710105, 710305
Abstract:
Methods, systems, apparatuses, and computer-readable media for controlling components connected to and/or otherwise associated with a data bus are presented. According to one or more aspects of the disclosure, a plurality of processing devices having data bus management capability and at least one data bus associated with the plurality of processing devices may be identified. Subsequently, an inter-processor communication (IPC) layer for communication between the plurality of processing devices and the at least one data bus may be established over a messaging layer utilized by the at least one data bus. At least one component associated with the at least one data bus may then be controlled via the IPC layer using at least one of the plurality of processing devices.

System And Method Of Sending Data Via A Plurality Of Data Lines On A Bus

View page
US Patent:
20130156044, Jun 20, 2013
Filed:
Dec 13, 2012
Appl. No.:
13/714140
Inventors:
Magesh Hariharan - San Diego CA, US
Julio Arceo - San Diego CA, US
Suren Mohan - San Diego CA, US
Aris Balatsos - Markham, CA
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H04L 12/56
US Classification:
370438, 370431, 370458, 370463
Abstract:
A method includes sending data from a first serial low-power inter-chip media bus (SLIMbus) component to a second SLIMbus component. The method further includes sending the data via at least a first SLIMbus data line of a plurality of SLIMbus data lines.

Multi-Channel Audio Alignment Schemes

View page
US Patent:
20160142454, May 19, 2016
Filed:
Nov 14, 2014
Appl. No.:
14/541557
Inventors:
- San Diego CA, US
Lior Amarilio - Yokneam, IL
Julio Arceo - San Diego CA, US
Aris Balatsos - Markham, CA
Hans Georg Gruber - San Diego CA, US
International Classification:
H04L 29/06
H04R 3/12
Abstract:
Multi-channel audio alignment schemes are disclosed. One aspect of the present disclosure provides for accumulation of audio samples across multiple related audio channels at an audio source. Related audio channels indicate their interrelatedness, and when all the related audio channels have data to transmit, the source releases the data onto the time slots of the Serial Low-power Inter-chip Media Bus (SLIMbus), such that the related audio channels are within a given segment window of the time slot. This accumulation is repeated at the boundary of every segment window. Similarly, accumulation may be performed at the audio sink. Components within the audio sink may only read received data if status signals from all related sinks indicate that predefined thresholds have been reached. By providing such accumulation options, audio fidelity is maintained across multiple audio data channels.

Multi-Channel Audio Alignment Schemes

View page
US Patent:
20160142455, May 19, 2016
Filed:
Nov 14, 2014
Appl. No.:
14/541577
Inventors:
- San Diego CA, US
Lior Amarilio - Yokneam, IL
Julio Arceo - San Diego CA, US
Aris Balatsos - Markham, CA
Hans Georg Gruber - San Diego CA, US
International Classification:
H04L 29/06
H04R 3/12
Abstract:
Multi-channel audio alignment schemes are disclosed. One aspect of the present disclosure provides for accumulation of audio samples across multiple related audio channels at an audio source. Related audio channels indicate their interrelatedness, and when all the related audio channels have data to transmit, the source releases the data onto the time slots of the Serial Low-power Inter-chip Media Bus (SLIMbus), such that the related audio channels are within a given segment window of the time slot. This accumulation is repeated at the boundary of every segment window. Similarly, accumulation may be performed at the audio sink. Components within the audio sink may only read received data if status signals from all related sinks indicate that predefined thresholds have been reached. By providing such accumulation options, audio fidelity is maintained across multiple audio data channels.
Control profile
Julio Arceo from San Diego, CA, age ~54 Get Report