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Julian M Kain

from Longmont, CO
Age ~43
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Also known as:
Julian Michael Kain, Michael J Kain, Kain Kain, Jullan Kain
Phone and address:
2129 Seaway Ct, Longmont, CO 80503
Related to:
Justin R Plank, 43Arthur Mazman, 94Eileen K Szypko, 68Peter Kain, 70Mary E Kain, 62John Kain, 64
Connected to:
Alexander C Kain, 45Aron Z Kain, 64Ashlie L Kain, 36Brenda J Kain, 60Crystal A Kain, 39Damon Kain, 29Denine J Kain, 66Dora M Kain, 56Doreen B Kain, 63Fred L Kain, 100

Julian Kain Phones & Addresses

  • 2129 Seaway Ct, Longmont, CO 80503
  • Saint Paul, MN
  • Sunnyvale, CA
  • Los Gatos, CA
  • Campbell, CA
  • Winter Park, FL
  • Tarpon Springs, FL
  • Ormond Beach, FL
  • 200 Winchester Cir APT H17, Los Gatos, CA 95032

Work

Company: Lockheed martin Jun 2005 to Jul 2007 Position: Asic and fpga design engineer

Education

Degree: Master of Science, Masters School / High School: Santa Clara University 2006 to 2010 Specialities: Computer Engineering

Skills

Fpga • Xilinx • Cloud Computing • Acceleration • Pcie • Opencl • Cuda • Rtl Design • Digital Logic • Systemverilog • Verilog • Computer Architecture • Hardware Architecture • Simulations • Functional Verification • Logic Synthesis • Static Timing Analysis • Hardware Validation • Serdes • Ethernet • Interlaken • Sfi • Team Leadership • Cross Functional Coordination • Technical Documentation • C • Embedded Systems • Python • Assembly Language • Alveo • Sdaccel • Sdx • Faas • Hardware Emulation

Industries

Computer Hardware

Resumes

Resumes

Julian Kain Photo 1

Principal Engineer

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Location:
2129 Seaway Ct, Longmont, CO 80503
Industry:
Computer Hardware
Work:
Lockheed Martin Jun 2005 - Jul 2007
Asic and Fpga Design Engineer
Lockheed Martin Jan 2001 - May 2005
Computer Engineering Student Intern
Xilinx Jan 2001 - May 2005
Principal Engineer
Education:
Santa Clara University 2006 - 2010
Master of Science, Masters, Computer Engineering University of Central Florida 2000 - 2005
Bachelors, Bachelor of Science, Computer Engineering Spruce Creek High School 1996 - 2000
Skills:
Fpga
Xilinx
Cloud Computing
Acceleration
Pcie
Opencl
Cuda
Rtl Design
Digital Logic
Systemverilog
Verilog
Computer Architecture
Hardware Architecture
Simulations
Functional Verification
Logic Synthesis
Static Timing Analysis
Hardware Validation
Serdes
Ethernet
Interlaken
Sfi
Team Leadership
Cross Functional Coordination
Technical Documentation
C
Embedded Systems
Python
Assembly Language
Alveo
Sdaccel
Sdx
Faas
Hardware Emulation

Publications

Us Patents

Method And Apparatus For Controlling An Operating Mode For An Embedded Ethernet Media Access Controller

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US Patent:
8284801, Oct 9, 2012
Filed:
Jan 26, 2010
Appl. No.:
12/693988
Inventors:
Mehulkumar R. Vashi - San Jose CA, US
Robert Yin - Castro Valley CA, US
Jayant Mittal - San Jose CA, US
Nicholas McKay - Edinburgh, GB
Julian Kain - Sunnyvale CA, US
Martin B. Rhodes - Peebles, GB
Mark R. Nethercot - Peebles, GB
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H04J 3/16
US Classification:
370470, 370252, 370465, 370471
Abstract:
Method and apparatus for controlling an operating mode of an Ethernet media access controller (MAC) embedded in a programmable device is described. In some examples, a configuration circuit is configured to receive a configuration signal from configuration memory of the programmable device and a host signal from a host bus of the programmable device, and configured to output a control length check disable signal the value of which depends on the value of at least one of the configuration signal or the host signal. A parameter check circuit is configured to receive a control signal derived from at least one of the control length check disable signal or the configuration signal, and configured to selectively disable checking a length of each control frame in frames received by the Ethernet MAC based on a value of the control signal.

Clock Domain Boundary Crossing Using An Asynchronous Buffer

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US Patent:
20140089718, Mar 27, 2014
Filed:
Sep 24, 2012
Appl. No.:
13/625108
Inventors:
- San Jose CA, US
Julian M. Kain - Sunnyvale CA, US
Assignee:
XILINX, INC. - San Jose CA
International Classification:
G06F 1/04
US Classification:
713500
Abstract:
An apparatus includes a plurality of channels, where each of the channels includes an asynchronous buffer, a latency determination block, a tap selection circuit, and a variable delay. A latency locator is configured to identify a longest latency from among the channels and is coupled to provide the longest latency to the tap selection circuit of each of the channels. For each of the channels: the latency determination block is coupled to the asynchronous buffer to determine a latency value for the asynchronous buffer; the tap selection circuit is coupled to receive the latency value and the longest latency; the tap selection circuit is coupled to the variable delay; and the tap selection circuit is configured to select a tap of taps of the variable delay responsive to the latency value and the longest latency.
Control profile
Julian M Kain from Longmont, CO, age ~43 Get Report