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Julia T Purtell

from Menlo Park, CA
Age ~64
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Also known as:
Julia H Purtell, Yulia Purtell, Julia Plotnikova, Julia Plotnikoy, Yulia Plotnikova, Julia A
Phone and address:
141 Stanford Ave, Menlo Park, CA 94025
(650) 854-3448
Related to:
Shane Sabicer, 59David SabicerDavid Sabicer, 35
Connected to:
Brandon T Purtell, 35Courtney Purtell, 30Gene M Purtell, 51Louise M Purtell, 103Andree Purter, 52Michael J Purter, 62Nichelle Purter, 53Paul F Purter, 88Tametha C Purter, 50Tiffany Purtilar, 39

Julia Purtell Phones & Addresses

  • 141 Stanford Ave, Menlo Park, CA 94025 (650) 854-3448 (650) 854-3697 (650) 854-3753
  • Riverside, CA
  • Palo Alto, CA
  • Mountain View, CA
  • San Francisco, CA
  • Santa Clara, CA
  • 141 Stanford Ave, Menlo Park, CA 94025 (650) 814-3752

Work

Position: Food Preparation and Serving Related Occupations

Emails

k***[email protected]

Resumes

Resumes

Julia Purtell Photo 1

Thermal Engineer At Microsoft

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Position:
Thermal Engineer at Microsoft
Location:
San Francisco Bay Area
Industry:
Computer Hardware
Work:
Microsoft
Thermal Engineer
Sun Microsystems 1997 - 2006
Thermal Engineer
Julia Purtell Photo 2

Julia Purtell

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Location:
San Francisco Bay Area
Industry:
Computer Software
Julia Purtell Photo 3

Julia Purtell

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Location:
San Francisco Bay Area
Industry:
Computer Hardware

Publications

Us Patents

Reliability Aware Thermal Design

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US Patent:
20150261901, Sep 17, 2015
Filed:
Jun 27, 2014
Appl. No.:
14/318221
Inventors:
- Redmond WA, US
Tung Thanh Nguyen - San Jose CA, US
Brian Keith Langendorf - Benicia CA, US
Julia Purtell - Menlo Park CA, US
Rune Hartung Jensen - Cupertino CA, US
Ranjit Gannamani - San Jose CA, US
Amit Prabhakar Marathe - Sunnyvale CA, US
International Classification:
G06F 17/50
Abstract:
Embodiments are disclosed that relate to implementing semiconductor device cooling systems that leverage awareness of regional voltage and temperature reliability risk considerations. For example, one disclosed embodiment provides a method of implementing a cooling system configured to cool an integrated circuit. The method involves first determining a heat dissipation factor that would reduce each region of the integrated circuit to a reduced temperature in order to maintain an overall failure rate. An analysis is then performed, using an insight about the relative reliability risk of elevated voltage and temperatures, to identify a region of the integrated circuit whose temperature can be permitted to rise without exceeding the overall failure rate, thereby permitting implementation of a cooling system with a reduced heat dissipation factor.
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Julia T Purtell from Menlo Park, CA, age ~64 Get Report