Joseph A Versaggi

20200185374, Jun 11, 2020

Dec 10, 2018

16/214450

- Grand Cayman, KY
Bipul C. Paul - Mechanicville NY, US
Joseph Versaggi - Galway NY, US

H01L 27/02
H01L 27/105
G11C 5/06
H01L 21/768
H01L 43/12
H01L 45/00

Structures for a non-volatile memory and methods for fabricating such structures. An active array region of a memory structure includes a plurality of active bitcells and a wordline. Dummy bitcells of the memory structure are arranged in a column within the active array region. An interconnect structure includes a metallization level having a wordline strap that extends across the active array region and that is arranged over the active array region.

20190279990, Sep 12, 2019

Mar 9, 2018

15/917027

- Grand Cayman, KY
Joseph Versaggi - Galway NY, US
Steven Bentley - Menands NY, US

H01L 27/11
G11C 11/412
G11C 11/419
H01L 51/05
H01L 29/78
H01L 29/06
H01L 27/28

Structures for a bitcell of a two-port static random access memory (SRAM) and methods for forming a structure for a bitcell of a two-port SRAM. A storage element of the SRAM includes a first pull-up (PU) vertical-transport field-effect transistor (VTFET) with a fin, a first pull-down (PD) VTFET with a fin that is aligned in a first row with the fin of the first PU VTFET, a second PU VTFET with a fin, and a second PD VTFET with a fin that is aligned in a second row with the fin of the second PU VTFET. The structure further includes a read port coupled with the storage element. The read port includes a read port pull-down (RPD) VTFET with a fin and a read port access (RPG) VTFET with a fin that is aligned in a third row with the fin of the RPG VTFET.

20180323117, Nov 8, 2018

May 8, 2017

15/589126

- GRAND CAYMAN, KY
HAJIME TERAZAWA - MALTA NY, US
JOSEPH VERSAGGI - GALWAY NY, US

GLOBALFOUNDRIES INC. - GRAND CAYMAN

H01L 21/66
H01L 27/11

Disclosed are an in-kerf test structure and testing method for testing an on-chip device. The structure includes at least one test component with at least one test device and adjoining dummy devices connected to the test device. Each adjoining dummy device has proximal node(s) directly connected to a test device and distal node(s) that are not directly connected to a test device. The nodes of each test device and the distal nodes of each adjoining dummy device are connected to input/output pads. During testing the input/output pads are used to bias the nodes of a selected test device as well as the distal node(s) of any adjoining dummy device. By biasing the distal node(s) of an adjoining dummy device, random accumulation of potential thereon is avoided and current contributions from the adjoining dummy device(s) to a current measurement taken from the selected test device can be accurately determined.