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Joseph R Verock

from Austin, TX
Age ~50
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Also known as:
Joe Verock
Phone and address:
9904 Whitley Bay Dr, Austin, TX 78717
Related to:
Craig R Campbell, 49Jeffrey Stuart Carver, 84
Connected to:
John D Veroeven, 54Amy E Veroff, 75David R Veroff, 62Robert Veroff, 61Katie M Veroline, 37Andrew P Veron, 44Todd B Veron, 66Carole M Verona, 81Claudia Verona, 38Fabienne Verona, 58

Joseph Verock Phones & Addresses

  • 9904 Whitley Bay Dr, Austin, TX 78717
  • 12100 Metric Blvd, Austin, TX 78758 (512) 215-9750
  • 11915 Stonehollow Dr, Austin, TX 78758 (512) 671-8354 (512) 671-8356
  • 2801 Wells Branch Pkwy, Austin, TX 78728 (512) 671-8354 (512) 671-8356
  • Acton, ME
  • Burke, VA
  • Rochester, NY

Industries

Computer Hardware

Resumes

Resumes

Joseph Verock Photo 1

Joseph Verock

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Location:
Austin, Texas Area
Industry:
Computer Hardware

Publications

Us Patents

Invention To Allow Multiple Layouts For A Schematic In Hierarchical Logical-To-Physical Checking On Chips

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US Patent:
6571374, May 27, 2003
Filed:
Feb 28, 2000
Appl. No.:
09/514563
Inventors:
Stephen Larry Runyon - Pflugerville TX
Robert T. Sayah - Poughkeepsie NY
Joseph Roland Verock - Austin TX
Steven Eugene Washburn - Poughquag NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
716 5, 716 4
Abstract:
An EQUATE property is introduced into the layout cell data for a layout design to identify the schematic to which the layout design corresponds. Rather than exploding the layout cell up to the next level for flat checking because the equivalent schematic is not known, the layout cell instances may then be checked hierarchically, with one instance checked internally for compliance with design rules and the like while the remaining instances are merely checked for proper connection to neighboring cells. New layout cell designs may therefore be created as the need arises during layout without requiring schematic checking tools to be rerun.

Invention To Allow Hierarchical Logical-To-Physical Checking On Chips

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US Patent:
6567958, May 20, 2003
Filed:
Feb 28, 2000
Appl. No.:
09/514564
Inventors:
Stephen Larry Runyon - Pflugerville TX
Joseph Roland Verock - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 945
US Classification:
716 5, 716 4
Abstract:
Layout cells having the same name as a corresponding schematic are checked hierarchically, with a single instance of a particular layout cell being checked internally for compliance with design rules and the like while remaining instances are merely checked for proper connection to neighboring cells. Layout cells which are not named the same as any schematic are automatically exploded for flat checking at the transistor level. Thus hierarchical checking is preserved for those layout cell instances named for the corresponding schematic, which should be the large majority of cell instances in any given integrated circuit, while cell instances meeting special layout requirements, which should be a small number of cases, are supported for any given schematic.
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Joseph R Verock from Austin, TX, age ~50 Get Report