Joseph J Jamann

8281266, Oct 2, 2012

Feb 3, 2009

12/365010

Joseph J. Jamann - Nazareth PA, US
James C. Parker - Zionsville PA, US
Vishwas M. Rao - Breinigsville PA, US

Agere Systems LLC - Wilmington DE

G06F 17/50

716108, 716109

Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional IC design that meets the performance objectives by employing a unitless performance/power quantifier as a metric to gauge a degree of optimization thereof and (6) performing a timing signoff of the layout at the optimization target voltage.

8307324, Nov 6, 2012

Aug 18, 2011

13/212427

Joseph J. Jamann - Nazareth PA, US
James C. Parker - Zionsville PA, US
Vishwas M. Rao - Breinigsville PA, US

Agere Systems LLC - Wilmington DE

G06F 17/50

716132, 716136, 703 14

One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing representative benchmark circuits for a clock path, a data path and a flip-flop path, (2) establishing at least one standard sensitization and measurement rule for delay and power for the representative benchmark circuits and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation, (5) writing the data to a databank and (6) parsing and interpreting the data to produce at least one report.

8332792, Dec 11, 2012

Jul 14, 2010

12/836274

Alexander Tetelbaum - Hayward CA, US
Joseph Jamann - Nazareth PA, US
Rich Laubhan - Windsor CO, US
Bruce Zahn - Allentown PA, US

LSI Corporation - Milpitas CA

G06F 17/50

716113, 716108, 716114

An apparatus and a method of generating a flexible ramptime limit for an electronic circuit, a computer program product that performs the same method, and a method of manufacturing an electronic circuit employing a flexible ramptime limit is disclosed. In one embodiment, the method for generating a flexible ramptime limit includes: (1) calculating a frequency based ramptime limit for the electronic circuit, (2) obtaining a library based ramptime limit for the electronic circuit, (3) determining a minimum ramptime limit between the frequency based ramptime limit and the library based ramptime limit and (4) selecting the minimum ramptime limit as the flexible ramptime limit.

8341573, Dec 25, 2012

Oct 15, 2010

12/905301

Vishwas M. Rao - Breinigsville PA, US
Joseph J. Jamann - Nazareth PA, US
James C. Parker - Zionsville PA, US

LSI Corporation - Milpitas CA

G06F 9/455
G06F 17/50

716108, 716106, 716113, 716118, 703 19

A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget.

8522179, Aug 27, 2013

Feb 6, 2012

13/367094

William R. Griesbach - Pocono Lake PA, US
Vishwas Rao - Breinigsville PA, US
Joseph J. Jamann - Nazareth PA, US

LSI Corporation - Milpitas CA

G06F 17/50

716108, 716102, 716103, 716104, 716105

A system for, and method of, generating block timing constraints and a timing model. In one embodiment, the system includes a hierarchical modeling tool configured to: (1) generate a model file, (2) receive at least one abstracted view margin, at least one timing environment margin and at least one operational margin for inclusion in the model file, (3) generate block implementation timing constraints employing the at least one timing environment margin and the at least one operational margin and (4) generate a block timing model employing the at least one abstracted view margin and the at least one operational margin.

8543951, Sep 24, 2013

Oct 11, 2012

13/649909

Joseph J. Jamann - Allentown PA, US
James C. Parker - Allentown PA, US

LSI Corporation - Milpitas CA

G06F 9/455
G06F 17/50

716108, 716106, 716113, 716118, 703 19

A method of designing a model of an integrated circuit block, an electronic design automation tool and a non-transitory computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating an input and output timing budget for the block based on design constraints of the block and a netlist of the block, (2) updating the input and output timing budget with clock customization data based on designer knowledge of the integrated circuit and (3) providing the model for the block based on the update of the input and output timing budget, wherein the model represents clock information of the block separately from data path information of the block.

20090281772, Nov 12, 2009

Feb 3, 2009

12/365084

Joseph J. Jamann - Nazareth PA, US
James C. Parker - Zionsville PA, US
Vishwas M. Rao - Breinigsville PA, US

Agere Systems, Inc. - Allentown PA

G06F 17/50

703 1, 703 14

One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing at least one representative benchmark circuit, (2) establishing standard sensitization and measurement rules for delay and power for the at least one representative benchmark circuit and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation and (5) parsing and interpreting the data to produce at least one report.

20130055175, Feb 28, 2013

Aug 30, 2012

13/599549

Joseph J. Jamann - Nazareth PA, US
James C. Parker - Zionsville PA, US
Vishwas M. Rao - Breinigsville PA, US

G06F 17/50

716103, 716136

Various embodiments of methods of designing an integrated circuit (IC) are provided herein. One embodiment of one such method includes: (1) generating a functional IC design, (2) determining a target clock rate for the functional IC design, (3) generating a netlist from the functional IC design that meets the target clock rate, (4) determining a unitless performance/power quantifier from the netlist, (5) attempting to increase the unitless performance/power quantifier by changing at least one of a speed, an area and a power consumption in at least some noncritical paths in the netlist, wherein the attempting is performed by a processor and (6) generating a layout of the IC from the netlist.