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Joseph R Foerstel

from Valencia, CA
Age ~93
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Also known as:
Joseph W Foerstel, Jos R Foerstel, Joe R Foerstel, Joeseph Foerstel
Phone and address:
23800 Rotunda Rd, Santa Clarita, CA 91355
Related to:
Carmela M Chhuon, 47Michael FoerstelRosie E FoerstelNereza M Foerstel, 56
Connected to:
Brian P Foerstel, 28Bryan E Foerster, 47Caroline E Foerster, 62Cecilia N Foerster, 30Claudia M Foerster, 95Danielle V Foerster, 37Deborah G Foerster, 55Elroy H Foerster, 88Joan A Foerstel, 87John Foerster, 62

Joseph Foerstel Phones & Addresses

  • 23800 Rotunda Rd, Valencia, CA 91355
  • Santa Clarita, CA
  • Sunnyvale, CA

Work

Company: Integra technologies silicon valley Sep 2017 Position: Vice president of operations for test and reliability

Education

Degree: Bachelors, Bachelor of Science School / High School: California Polytechnic State University - San Luis Obispo 1983 to 1988 Specialities: Engineering

Skills

Semiconductors • Testing • Semiconductor Industry • Ic • Electronics • Mixed Signal • Test Engineering • Asic • Pcb Design • Analog • Dft • Fpga • Hardware Architecture • Manufacturing Engineering • Signal Integrity • Soc • Debugging • Verilog • Hardware • Altera • Serdes • Tcl • Quality Control • Operations Management • Fmea • Field Programmable Gate Arrays • System on A Chip • Vendor Management • Third Party Vendor Management • Test Automation • Pcb Layout Design • Printed Circuit Board Manufacturing • Cost Management • Electronics Packaging • Department Budget Management • Material Handling • Start Up Environment • Continuous Improvement

Languages

English

Interests

Collecting Antiques • Exercise • Sweepstakes • Home Improvement • Donor • Reading • Gourmet Cooking • Sports • The Arts • Home Decoration • Cooking • Gardening • Outdoors • Electronics • Crafts • Music • Family Values • Movies • Collecting • Christianity • Kids • Parenting • Automobiles • Woodwork • Travel • Investing • Traveling

Industries

Semiconductors

Resumes

Resumes

Joseph Foerstel Photo 1

Vice President Of Operations For Test And Reliability

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Location:
3000 Mark Ave, Santa Clara, CA 95051
Industry:
Semiconductors
Work:
Integra Technologies Silicon Valley
Vice President of Operations For Test and Reliability
Corwil Technology Corporation Mar 2014 - Dec 11, 2016
General Manager, Cowil Test Division - Viko Labs
Corwil Technology Corporation Jul 2015 - Dec 11, 2016
Vice President of Test Operations
Altera Jul 2009 - Jun 2013
Senior Manager Hardware Development
Altera Jul 1, 2005 - Jul 1, 2009
Manager Manufacturing Engineering
Education:
California Polytechnic State University - San Luis Obispo 1983 - 1988
Bachelors, Bachelor of Science, Engineering
Skills:
Semiconductors
Testing
Semiconductor Industry
Ic
Electronics
Mixed Signal
Test Engineering
Asic
Pcb Design
Analog
Dft
Fpga
Hardware Architecture
Manufacturing Engineering
Signal Integrity
Soc
Debugging
Verilog
Hardware
Altera
Serdes
Tcl
Quality Control
Operations Management
Fmea
Field Programmable Gate Arrays
System on A Chip
Vendor Management
Third Party Vendor Management
Test Automation
Pcb Layout Design
Printed Circuit Board Manufacturing
Cost Management
Electronics Packaging
Department Budget Management
Material Handling
Start Up Environment
Continuous Improvement
Interests:
Collecting Antiques
Exercise
Sweepstakes
Home Improvement
Donor
Reading
Gourmet Cooking
Sports
The Arts
Home Decoration
Cooking
Gardening
Outdoors
Electronics
Crafts
Music
Family Values
Movies
Collecting
Christianity
Kids
Parenting
Automobiles
Woodwork
Travel
Investing
Traveling
Languages:
English

Business Records

Name / Title
Company / Classification
Phones & Addresses
Joseph Foerstel
Snr Manufacturing Engineer
Altera
Semiconductors · Mfg of Semiconductors and Related Devices · Mfg Semiconductors · Mfg Semiconductors and Related Devices · Mfg Semiconductors Software Development · Mfg Semiconductor Chips & Related Software · Semiconductor Devices (Manufac · Semiconductor and Related Device Manufacturing
101 Innovation Dr, San Jose, CA 95134
101 Innovation Dr Attn Tax, San Jose, CA 95134
Suite SUITE J, Phoenix, AZ 85021
131 Innovation Dr, San Jose, CA 95134
(408) 544-7000, (408) 544-7900, (408) 544-6410, (408) 428-0463

Publications

Us Patents

Elongated Bonding Pad For Wire Bonding And Sort Probing

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US Patent:
7091613, Aug 15, 2006
Filed:
Oct 31, 2003
Appl. No.:
10/699118
Inventors:
Jon M. Long - Livermore CA, US
Joseph W. Foerstel - Santa Clara CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01L 23/48
US Classification:
257758, 257736, 257760, 257774, 257780
Abstract:
An elongated bonding pad comprises two areas, a bonding area and an elongated probing area. The bonding area is located on the edge of an integrated circuit device for wire bonding. The elongated probing area is located on the inner area of the device. The long dimension of the elongated probing area is large enough for carrying a probing mark and the short dimension of the probing area is electrically and mechanically connected to the bonding area. Such elongated bonding pad can reduce the possibility of bonding wire open failures caused by wafer sort probing and increase the device's capacity of hosting more electrical components.

Touchdown Counter For Integrated Circuit Testers

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US Patent:
7330025, Feb 12, 2008
Filed:
Nov 23, 2005
Appl. No.:
11/286250
Inventors:
Ronald M. Beach - Pleasanton CA, US
James Stephen Paine - San Jose CA, US
Joseph W. Foerstel - Santa Clara CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G01R 31/28
US Classification:
3241581
Abstract:
A touch-down counter is provided that maintains a count of how many times integrated circuits are placed into contact with a contactor in a test handler. The test handler has a work press that places integrated circuits into contact with pogo pins in the contactor. The pins are subject to wear and should be maintained by periodic cleaning. The touch-down counter has a sensor such as a non-contact Hall effect sensor that is attached to the contactor. A magnet is affixed to the side of the work press. When the work press comes into the vicinity of the sensor, the sensor detects the presence of the magnet and registers a contactor touch-down event. A lifetime count of touch-down events may be displayed on the counter. When a recommended threshold value of touch-down events has been exceeded, a test system operator can remove the contactor from use for cleaning.

Apparatus For A Low-Cost Semiconductor Test Interface System

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US Patent:
7768280, Aug 3, 2010
Filed:
Nov 15, 2007
Appl. No.:
11/941034
Inventors:
Adam J. Wright - Saratoga CA, US
Joseph W. Foerstel - Santa Clara CA, US
Mark Andrew Banke - San Jose CA, US
Ken A. Ito - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G01R 31/02
US Classification:
324754, 324755, 3241581
Abstract:
A system for testing a device under test (DUT), in which electrical coupling among a module board, a low profile connector, and, a DIB is established by applying a pressure on the module board toward the DUT, is provided. The system includes a test head bracket secured inside a test head, the test head bracket includes the module board having a first section including a plurality of connectors to couple a test analyzer to the module board, a second section including a plurality of contacts pads to electrically couple the module board to the DUT, and, a flexible board to enable the first section to be placed at an angle with respect to the second section. The test head bracket also includes a module board stiffener mechanically securing the first section and the second section to the test head and the low profile connector electrically couples the module board to the DUT.

Test Head Apparatus For Use In Electronic Device Test Equipment

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US Patent:
59492392, Sep 7, 1999
Filed:
Oct 31, 1996
Appl. No.:
8/739871
Inventors:
Saiid Rezvani - Los Gatos CA
J. Stephen Paine - San Jose CA
Joseph Foerstel - Santa Clara CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
G01R 3102
G01R 1073
US Classification:
324754
Abstract:
A test head apparatus for use in electronic device test equipment includes a test head with an annular test head body including a probe card carrier attachment region of a first circumference and a test electronic card storage region with a second circumference greater than the first circumference. The probe card carrier attachment region of the test head body is compatible with probe card carriers for existing test heads. The enlarged test electronic card storage region provides more space for electronic equipment, while providing more viewing area of the probe card. The apparatus also includes an improved probe card attachment configuration.

Surface Mount Chip Carrier

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US Patent:
55671772, Oct 22, 1996
Filed:
Jan 30, 1995
Appl. No.:
8/381005
Inventors:
Joseph W. Foerstel - Sunnyvale CA
Sandeep Vij - San Jose CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01R 2372
US Classification:
439526
Abstract:
An apparatus and method are disclosed to permit handling an electronic device (20) during programming, development, and other steps. The apparatus include a carrier (2) having a cavity (15) in which the electronic component is immobilized and protected during handling. The carrier cavity can have an opening that permits access to the electronic component. The carrier/device combination is inserted into a socket (35) which includes a plurality of leads (30) with associated contacts for making electrical connection with the electronic component leads (21). The leads of the socket have a footprint identical to that of the electronic component.

Surface Mount Chip Carrier

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US Patent:
53014162, Apr 12, 1994
Filed:
Apr 24, 1992
Appl. No.:
7/874281
Inventors:
Joseph W. Foerstel - Sunnyvale CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01R 2372
US Classification:
29593
Abstract:
An apparatus and method are disclosed to permit handling an electronic device (20) during programming, development, and other steps. The apparatus include a carrier (2) having a cavity (15) in which the electronic component is immobilized and protected during handling. The carrier cavity can have an opening that permits access to the electronic component. The carrier/device combination is inserted into a socket (35) which includes a plurality of leads (30) with associated contacts for making electrical connection with the electronic component leads (21). The leads of the socket have a footprint identical to that of the electronic component.

Apparatus And Method For Loading An Electronic Component Into A Carrier

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US Patent:
58453857, Dec 8, 1998
Filed:
Oct 31, 1996
Appl. No.:
8/742055
Inventors:
Joseph Foerstel - Santa Clara CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
B23P 1100
US Classification:
29464
Abstract:
A method of loading an electronic component into a carrier includes the step of setting an electronic component onto a pedestal including a pedestal post. A carrier with a clip is positioned over the pedestal. The pedestal post is forced against the clip such that the clip is in a retracted position that allows the electronic component to be positioned in the carrier. The pedestal post is then removed from the clip so that the electronic component is secured in the carrier by the clip.
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Joseph R Foerstel from Valencia, CA, age ~93 Get Report