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Joseph Mathew Chalil

from Lake Worth, FL
Age ~51
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Also known as:
Joseph Matthew Chalil, Joseph M Chalil, Joseph Dr Chalil, Joseph D Chalil, Joseph R Chalil, Mathew J Chalil, Joe Chalil, Rajesh Joseph, Joseph Rajesh
Phone and address:
6219 Vireo Ct, Lake Worth, FL 33463
(586) 362-1010
Related to:
Jerold Wilson, 60Marva Joseph, 51Ernestine Wilson, 88Jaimon Cyriac, 58
Connected to:
Jim Chalil, 51Margaret M Chalin, 70Julia C Chalios, 58Nicole M Chalitta, 37Kiran Chalivendra, 44Casey J Chalk, 41Catherine W Chalk, 79Douglas M Chalk, 60Ginger T Chalk, 73Jacob Chalk, 125

Joseph Chalil Phones & Addresses

  • 6219 Vireo Ct, Lake Worth, FL 33463 (586) 362-1010
  • 7285 Millrock Ave, Utica, MI 48317 (586) 254-4042 (586) 580-3768
  • Shelby Township, MI
  • Brookfield, CT
  • 11647 Hovey St, Warren, MI 48089 (586) 427-4442 (810) 427-4442 (586) 427-4462
  • Miami, FL
  • Macomb, MI

Public records

Vehicle Records

Joseph Chalil

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Address:
9 Nature Ln, Brookfield, CT 06804
Phone:
(586) 668-3236
VIN:
2CNFLNEW2A6352979
Make:
CHEVROLET
Model:
EQUINOX
Year:
2010

Publications

Us Patents

Method Of Forming Monolithic Cmos-Mems Hybrid Integrated, Packaged Structures

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US Patent:
8101458, Jan 24, 2012
Filed:
Aug 12, 2010
Appl. No.:
12/855107
Inventors:
G. Krishna Kumar - Troy MI, US
Nishit A. Choksi - Troy MI, US
Joseph M. Chalil - Shelby Township MI, US
Assignee:
Advanced Microfab, LLC - Ann Arbor MI
International Classification:
H01L 21/50
US Classification:
438106, 438 51, 438 55, 438E21449
Abstract:
A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing a semiconductor substrate with pre-fabricated cmos circuits on the front side and a polished back-side with through substrate conductive vias; forming at least one opening in the polished backside of the semiconductor substrate by appropriately protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one prefabricated mems, nems or cmos chip on the filler material, the chip including a front face and a bare back face with the prefabricated mems/nems chips containing mechanical and dielectric layers; applying at least one planarization layer overlying the substrate, filler material and the chip; forming at least one via opening on a portion of the planarization layer interfacing pads on the chip and the through substrate conductive vias; applying at least one metallization layer overlying the planarization layer on the substrate and the chip connecting the through substrate conductive vias to the at least one chip; applying at least one second insulating layer overlying the metallization layer; performing at least one micro/nano fabrication etching step to release the mechanical layer on the prefabricated mems/nems chips; positioning protective cap to package the integrated device over the mems/nems device area on the pre-fabricated chips.

Method Of Forming Monolithic Cmos-Mems Hybrid Integrated, Packaged Structures

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US Patent:
8101469, Jan 24, 2012
Filed:
Mar 26, 2010
Appl. No.:
12/732689
Inventors:
G. Krishna Kumar - Troy MI, US
Nishit A. Choksi - Troy MI, US
Joseph M. Chalil - Shelby Township MI, US
Assignee:
Advanced Microfab, LLC - Ann Arbor MI
International Classification:
H01L 21/44
US Classification:
438123, 438 51, 438 55, 438106, 438E21002
Abstract:
A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate.

Method Of Forming Monolithic Cmos-Mems Hybrid Integrated, Packaged Structures

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US Patent:
7989248, Aug 2, 2011
Filed:
Jul 2, 2009
Appl. No.:
12/497107
Inventors:
G. Krishna Kumar - Troy MI, US
Nishit A. Choksi - Troy MI, US
Joseph M. Chalil - Shelby Township MI, US
Assignee:
Advanced Microfab, LLC - Troy MI
International Classification:
H01L 21/00
US Classification:
438 51, 438 50, 438 53
Abstract:
A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate.

Flexible Penetrating Electrodes For Neuronal Stimulation And Recording And Method Of Manufacturing Same

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US Patent:
20110054579, Mar 3, 2011
Filed:
Aug 25, 2009
Appl. No.:
12/547191
Inventors:
G. Krishna Kumar - Troy MI, US
Joseph M. Chalil - Shelby Twp. MI, US
Nishit A. Choksi - Troy MI, US
Assignee:
Advanced Microfab, LLC - Troy MI
International Classification:
A61N 1/05
B44C 1/22
US Classification:
607116, 216 13
Abstract:
A flexible penetrating array for neuronal applications includes an insulating layer. A conductive layer is formed on the insulating layer. A flexible polymer substrate is formed on the conductive layer; the polymer substrate includes defined penetrating electrodes. A first metallization layer is formed on the polymer substrate. A second flexible polymer layer is formed on the first metallization layer. A second metallization layer is formed on the second flexible polymer layer. A third flexible polymer layer is formed on the second metallization layer. The third flexible polymer layer is patterned to expose the second metallization layer that is integrated with the out of plane conductive layer and first metallization layer. Also disclosed is a method of forming the array.
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Joseph Mathew Chalil from Lake Worth, FL, age ~51 Get Report