Joseph James Balardeta

6502231, Dec 31, 2002

May 31, 2001

09/871473

Simon S. Pang - San Diego CA
Rimon Shookhtim - Cardiff by the Sea CA
Joseph J. Balardeta - Carlsbad CA
Gary Wong - San Diego CA

Applied Micro Circuits Corporation - San Diego CA

G06F 1750

716 17, 716 14

A system and method are provided for forming a template cell on the input/output (I/O) surface of an integrated circuit (IC). The first metal layer of the cell includes a plurality of parallel bus lines extending from one edge of the cell to the other. A second underlying metal layer includes bus lines extending in an orthogonal direction to the first layer lines. A signal routing layer underlies the second metal layer, with a routing channel located around the edges of the cell, and ESD and output buffer circuits placed inside of the routing channel. The bus lines of the first and second metal layers, and the routing channel of the signal routing layer, have connection areas so that connections are formed by abutting the cells. Each cell also includes a flip-chip solder pad overlying the first metal layer that can be connected by a via to either the first or second metal layer.

6566967, May 20, 2003

Feb 26, 2002

10/085458

Sudhaker Reddy Anumula - San Diego CA
Joseph J. Balardeta - Carlsbad CA
Wei Fu - San Diego CA
Paul Vanderbilt - Encinitas CA
Mehmet Mustafa Eker - Santee CA

Applied Micro Circuits Corporation - San Diego CA

H03L 700

331 11

A configurable PLL architecture having multiple detection elements. The configurable PLL circuit includes a first detector for providing a first differential signal, a second detector for providing a second differential signal, a third detector for providing a third differential signal, and a selection circuit for enabling at least one of the first, second and third detectors. The PLL circuit also includes a multiplexer for receiving at least one differential signal from a corresponding enabled detector, and for providing a multiplexed differential signal output. In operation, an operating mode is selected, and one or more detectors are enabled for operation with one or more input reference signals. The outputs of the enabled detectors is received by the multiplexer to complete the operation of the selected operating mode.

6538520, Mar 25, 2003

Oct 18, 2001

09/982156

Allen Carl Merrill - Encinitas CA
Joseph James Balardeta - Carlsbad CA
Wei Fu - San Diego CA
Mehmet Eker - Santee CA

Applied Micro Circuits Corporation - San Diego CA

H03B 1900

331 18, 331 1 A, 331 74, 331175, 327116, 327122, 327159

Circuitry for a phase locked loop (PLL) includes a first frequency doubler; a first equalizer having an input coupled to an output of the first frequency doubler; a second frequency doubler having an input coupled to an output of the first equalizer; and a second equalizer having an input coupled to an output of the second frequency doubler and an output which is fed into the PLL. Each frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The combination of the two frequency doublers in series quadruples the reference signal into the PLL, which allows the, PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter. Advantageously, controls for the selection of the initial reference signal are provided.

6545524, Apr 8, 2003

Feb 26, 2002

10/085613

Sudhaker Reddy Anumula - San Diego CA
Wei Fu - San Diego CA
Joseph J. Balardeta - Carlsbad CA
Paul Vanderbilt - Encinitas CA
Allen C. Merrill - Encinitas CA

Applied Micro Circuits Corporation - San Diego CA

H03K 1762

327407, 327415

A configurable multiplexing circuit and arrangement suited for phase locked loop applications. The multiplexing circuit includes an EX-OR element, a multiplexer element and a summer element. Each element is configured for receiving a particular type of detection signal output, as an input for one of multiple selectable multiplexing operations. The multiplexing circuit further includes a selection signal input, coupled to the EX-OR element, the multiplexer element and the summer element, for receiving a selection signal that enables one or more of the EX-OR element, the multiplexer element, and the summer element. Non-enabled elements are powered down to eliminate jitter and performance penalties.

6642781, Nov 4, 2003

Sep 6, 2002

10/236761

Mehmet M. Eker - Santee CA
Wei Fu - San Diego CA
Joseph J. Balardeta - Carlsbad CA

Applied Micro Circuits Corporation - San Diego CA

H03B 100

327555

A system and method have been provided for selectably equalizing an input signal to an integrated circuit (IC), to compensate for degradation in the transmission process. The selectable equalization circuit includes parallel equalizing and non-equalizing sections. When the equalizing section is engaged a resonant element modifies the circuit impedance to add a zero to the circuit transfer function. When the non-equalizing function is engaged, the equalizing section is disengaged without degrading gate capacitance, and the input signals are processed without a zero in the transfer function.

6657464, Dec 2, 2003

Apr 25, 2002

10/132425

Joseph James Balardeta - Del Mar CA
Allen Carl Merrill - Encinitas CA
Wei Fu - San Diego CA

Applied Micro Circuits Corporation - San Diego CA

H03L 706

327147, 327156, 327163, 327294, 331 11, 331DIG 2

A low-jitter phase-locked loop (PLL) circuit includes a reference signal generator and a PLL. The reference signal generator is configured to quadruple a frequency of a first reference signal to produce a second reference signal. The PLL includes a filter coupled in series with a voltage controlled oscillator (VCO), and a frequency phase detector configured to generate a first error signal based on a frequency difference between the second reference signal and a first divided VCO output signal. The PLL further includes a phase detector configured to generate a second error signal based on a phase difference between the second reference signal and a second divided VCO output signal at each rising and falling transition of the second reference signal. The PLL further includes a multiplexer configured for initially receiving the first error signal until the frequencies of the first divided VCO output signal feedback signal and the second reference signal match, and thereafter for receiving the second error signal, and to provide the first or second error signal to the filter.

6720806, Apr 13, 2004

Apr 25, 2002

10/132463

Allen Carl Merrill - Encinitas CA
Joseph James Balardeta - Del Mar CA
Sudhaker Reddy Anumula - San Diego CA

Applied Micro Circuits Corporation - San Diego CA

H03B 1900

327116, 327119, 327294

Circuitry for a phase locked loop (PLL) includes a reference signal input and a frequency doubler. The output of the frequency doubler is a second reference signal having a frequency that is approximately twice that of the initial reference signal, and which is fed into the PLL. The frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The frequency doubler can include one or more additional delay circuits in series after the first delay circuit, the output of which is provided to a multiplexer. The multiplexer includes a selection signal input for selecting an output from at least one of the delay circuits to be provided to the XOR circuit. The frequency doubler allows the PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter.

6725443, Apr 20, 2004

Oct 24, 2002

10/280978

Simon S. Pang - San Diego CA
Rimon Shookhtim - Cardiff by the Sea CA
Joseph J. Balardeta - Carlsbad CA
Gary Wong - San Diego CA

Applied Micro Circuits Corporation - San Diego CA

G06F 1750

716 17, 716 14

A system and method are provided for forming a template cell on the input/output (I/O) surface of an integrated circuit (IC). The first metal layer of the cell includes a plurality of parallel bus lines extending from one edge of the cell to the other. A second underlying metal layer includes bus lines extending in an orthogonal direction to the first layer lines. A signal routing layer underlies the second metal layer, with a routing channel located around the edges of the cell, and ESD and output buffer circuits placed inside of the routing channel. The bus lines of the first and second metal layers, and the routing channel of the signal routing layer, have connection areas so that connections are formed by abutting the cells. Each cell also includes a flip-chip solder pad overlying the first metal layer that can be connected by a via to either the first or second metal layer.