Search

Jong Hoon Shin

from San Ramon, CA
Age ~55
Get Report
Also known as:
Jong H Shin, Jonghoon Shin, John Hoon Shin, John H Shin, Shin Jong Hoon
Related to:
Mo Jung, 53Jungmo M Sung, 52
Connected to:
Adriana G Shin, 43Ahran Shin, 43Allen B Shin, 58Barbara J Shin, 86Bokyung Shin, 39Bora Shin, 43Bun Y Shin, 74Byung K Shin, 61Changhoon Shin, 37Christie Shin, 37

Jong Shin Phones & Addresses

  • San Ramon, CA
  • San Jose, CA
  • 4984 Severance Dr APT 230, San Jose, CA 95136

Professional Records

Lawyers & Attorneys

Jong Shin Photo 1

Jong Eun Shin - Lawyer

View page
Address:
Mmaa Building
(237) 818-746x (Office)
Licenses:
New York - Due to reregister within 30 days of birthday 2003
Education:
George Washington University National Law Center

Medicine Doctors

Jong Shin Photo 2

Jong T. Shin

View page
Specialties:
Acupuncturist
Work:
Chung Institute Of Integrated Medicine
110 Marter Ave STE 507, Moorestown, NJ 08057
(856) 222-4766 (phone), (856) 222-1137 (fax)
Education:
Medical School
Philadelphia College of Osteopathic Medicine
Graduated: 2004
Procedures:
Acupuncture
Conditions:
Gastroesophageal Reflux Disease (GERD)
Intervertebral Disc Degeneration
Lyme Disease
Languages:
English
Korean
Spanish
Description:
Dr. Shin graduated from the Philadelphia College of Osteopathic Medicine in 2004. He works in Moorestown, NJ and specializes in Acupuncturist. Dr. Shin is affiliated with Cooper University Hospital.

Business Records

Name / Title
Company / Classification
Phones & Addresses
Jong Shin
Manager
Surf City Squeeze
Fruit and Vegetable Markets
10123 N Wolfe Rd # K7, Cupertino, CA 95014
Website: surfcitysqueeze.com
Jong Shin
Professional Engineer
Lockheed Martin Corp
Aircraft
1111 Lockheed Martin Way, Sunnyvale, CA 94089
Jong Shin
Manager
Surf City Squeeze
Fruit and Vegetable Markets
10123 N Wolfe Rd # K7, Cupertino, CA 95014
Website: surfcitysqueeze.com
Jong Shin
Professional Engineer
Lockheed Martin Corp
Aircraft
1111 Lockheed Martin Way, Sunnyvale, CA 94089
Jong Shin
Principal
Pyung Chang Restaurante
Eating Place · Catering
4701 Telegraph Ave, Oakland, CA 94609
(510) 658-9040
Jong Shin
Manager
Surf City Squeeze
Fruit & Vegetable Markets
10123 N Wolfe Rd #K7, Cupertino, CA 95014
(408) 725-2613
Jong Nam Shin
President
BLUE STAR TECH CORPORATION
1200 Gough St #10A, San Francisco, CA 94109
Jong Shin
Managing
Pacific Smoothies, LLC
International · Business Services at Non-Commercial Site · Nonclassifiable Establishments
67 Clinton St, Redwood City, CA 94062

Publications

Us Patents

Methods For High Temperature Etching A High-K Material Gate Structure

View page
US Patent:
8501626, Aug 6, 2013
Filed:
Jun 25, 2008
Appl. No.:
12/146303
Inventors:
Wei Liu - San Jose CA, US
Eiichi Matsusue - Yokohama, JP
Meihua Shen - Fremont CA, US
Shashank Deshmukh - San Jose CA, US
Anh-Kiet Quang Phan - San Jose CA, US
David Palagashvili - Mountain View CA, US
Michael D. Willwerth - Campbell CA, US
Jong I. Shin - Santa Clara CA, US
Barrett Finch - San Jose CA, US
Yohei Kawase - Chiba, JP
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/302
H01L 21/461
C03C 15/00
C03C 25/68
US Classification:
438696, 216 41, 216 46, 216 51, 216 72, 438700, 438710, 438958
Abstract:
Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.

Methods For High Temperature Etching A High-K Gate Structure

View page
US Patent:
20130344701, Dec 26, 2013
Filed:
Jun 28, 2013
Appl. No.:
13/929969
Inventors:
Wei LIU - San Jose CA, US
Eiichi MATSUSUE - Yokohama, JP
Meihua SHEN - Fremont CA, US
Shashank C. DESHMUKH - San Ramon CA, US
Anh-Kiet Quang PHAN - San Jose CA, US
David PALAGASHVILI - Mountain View CA, US
Michael D. WILLWERTH - Campbell CA, US
Jong I. SHIN - Milpitas CA, US
Barrett FINCH - San Jose CA, US
Yohei KAWASE - Chiba, JP
International Classification:
H01L 21/3065
US Classification:
438715
Abstract:
Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.

Cmos-Mems Integrated Device Including Multiple Cavities At Different Controlled Pressures And Methods Of Manufacture

View page
US Patent:
20170183225, Jun 29, 2017
Filed:
Mar 16, 2017
Appl. No.:
15/461270
Inventors:
- San Jose CA, US
Jongwoo SHIN - Pleasanton CA, US
Jong Il SHIN - San Jose CA, US
Peter SMEYS - San Jose CA, US
Martin LIM - San Mateo CA, US
International Classification:
B81C 1/00
Abstract:
An integrated MEMS device comprises two substrates where the first and second substrates are coupled together and have two enclosures there between. One of the first and second substrates includes an outgassing source layer and an outgassing barrier layer to adjust pressure within the two enclosures. The method includes depositing and patterning an outgassing source layer and a first outgassing barrier layer on the substrate, resulting in two cross-sections. In one of the two cross-sections a top surface of the outgassing source layer is not covered by the outgassing barrier layer and in the other of the two cross-sections the outgassing source layer is encapsulated in the outgassing barrier layer. The method also includes depositing conformally a second outgassing barrier layer and etching the second outgassing barrier layer such that a spacer of the second outgassing barrier layer is left on sidewalls of the outgassing source layer

Mems-Cmos Device That Minimizes Outgassing And Methods Of Manufacture

View page
US Patent:
20170073217, Mar 16, 2017
Filed:
Dec 1, 2016
Appl. No.:
15/366495
Inventors:
- San Jose CA, US
Jong Il SHIN - San Jose CA, US
Jongwoo SHIN - Pleasanton CA, US
International Classification:
B81B 7/00
B81C 1/00
Abstract:
A MEMS device is disclosed. The MEMS device includes a first substrate. At least one structure is formed within the first substrate. The first substrate includes at least one first conductive pad thereon. The MEMS device also includes a second substrate. The second substrate includes a passivation layer. The passivation layer includes a plurality of layers. A top layer of the plurality of layers comprises an outgassing barrier layer. At least one second conductive pad and at least one electrode are coupled to the top layer. At least one first conductive pad is coupled to the at least one second conductive pad.

Cmos-Mems Integrated Device Including A Contact Layer And Methods Of Manufacture

View page
US Patent:
20160362296, Dec 15, 2016
Filed:
Jun 12, 2015
Appl. No.:
14/738645
Inventors:
- San Jose CA, US
Jongwoo SHIN - Pleasanton CA, US
Jong Il SHIN - San Jose CA, US
Peter SMEYS - San Jose CA, US
International Classification:
B81C 1/00
Abstract:
A method for forming a MEMS device is disclosed. The MEMS device includes a MEMS substrate and a base substrate. The MEMS substrate, where includes a handle layer, a device layer and an insulating layer in between. The method includes the sequential steps of: providing a standoff on the device layer; etching a via through the device layer and the insulating layer; providing a contact layer within the via, wherein the contact layer provides electrical connection between the device layer and the handle layer; providing a bonding layer on the standoff; and bonding the bonding layer to pads on the base substrate.

Mems-Cmos Device That Minimizes Outgassing And Methods Of Manufacture

View page
US Patent:
20160221819, Aug 4, 2016
Filed:
Jun 23, 2015
Appl. No.:
14/748012
Inventors:
- San Jose CA, US
Jong Il SHIN - San Jose CA, US
Jongwoo SHIN - Pleasanton CA, US
International Classification:
B81B 7/00
B81C 1/00
Abstract:
A MEMS device is disclosed. The MEMS device includes a first substrate. At least one structure is formed within the first substrate. The first substrate includes at least one first conductive pad thereon. The MEMS device also includes a second substrate. The second substrate includes a passivation layer. The passivation layer includes a plurality of layers. A top layer of the plurality of layers comprises an outgassing barrier layer. At least one second conductive pad and at least one electrode are coupled to the top layer. At least one first conductive pad is coupled to the at least one second conductive pad.

Film Induced Interface Roughening And Method Of Producing The Same

View page
US Patent:
20160115016, Apr 28, 2016
Filed:
Mar 24, 2015
Appl. No.:
14/667169
Inventors:
- San Jose CA, US
Martin Lim - San Mateo CA, US
Jong Il Shin - San Jose CA, US
Jongwoo Shin - Pleasanton CA, US
International Classification:
B81C 1/00
Abstract:
Various embodiments provide for a method for roughening a surface of a MEMs device or the surface of a CMOS surface. A first material can be deposited in a thin layer over a surface made of a second material. After heating, the first and second materials, they can partially melt and interdiffuse, forming an alloy. The first material can then be removed and the alloy is removed at the same time. The surface of the second material that is left behind has then been roughened due to the interdiffusion of the first and second materials.

Internal Barrier For Enclosed Mems Devices

View page
US Patent:
20160075554, Mar 17, 2016
Filed:
Sep 10, 2015
Appl. No.:
14/850860
Inventors:
- San Jose CA, US
Jongwoo SHIN - Pleasanton CA, US
Peter SMEYS - San Jose CA, US
Cerina ZHANG - Milpitas CA, US
Jong Il SHIN - San Jose CA, US
International Classification:
B81B 7/00
B81C 1/00
Abstract:
A MEMS device having a channel configured to avoid particle contamination is disclosed. The MEMS device includes a MEMS substrate and a base substrate. The MEMS substrate includes a MEMS device area, a seal ring and a channel. The seal ring provides for dividing the MEMS device area into a plurality of cavities, wherein at least one of the plurality of cavities includes one or more vent holes. The channel is configured between the one or more vent holes and the MEMS device area. Preferably, the channel is configured to minimize particles entering the MEMS device area directly. The base substrate is coupled to the MEMS device substrate.
Control profile
Jong Hoon Shin from San Ramon, CA, age ~55 Get Report