Jonathan G Pabustan

7434092, Oct 7, 2008

Feb 22, 2005

11/063316

Chih-Chieh Wang - Fremont CA, US
Jonathan G. Pabustan - San Lorenzo CA, US
Ben Sheen - Milpitas CA, US

Silicon Storage Techonology, Inc. - Sunnyvale CA

G06F 11/00

714 6, 714 5, 714 7, 714 8, 714 42

Redundantly repaired semiconductor memory and method in which the configuration data for the memory is stored in an area of the main memory array which is known to be free of bad bits, along with a signature code which serves as a pointer and verifies the validity of the configuration data. In one disclosed embodiment, the data is stored in a configuration memory which is divided into a plurality of areas of equal size and known starting addresses. The number of areas is greater than the number of permitted repairs, and the areas which do not contain defects are available for storing configuration data including device settings, repair information, and the like.

7668013, Feb 23, 2010

Feb 7, 2008

12/027654

Geeng-Chuan Michael Chern - Cupertino CA, US
Ben Sheen - Milpitas CA, US
Jonathan Pabustan - San Lorenzo CA, US
Prateep Tuntasood - San Jose CA, US
Der-Tsyr Fan - Ping-Jen, TW
Yaw Wen Hu - Cupertino CA, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C 16/04

36518517, 36518505, 36518529, 36518533

A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”).

7835190, Nov 16, 2010

Aug 12, 2008

12/190409

Vishal Sarin - Cupertino CA, US
Dzung Nguyen - Fremont CA, US
Jonathan Pabustan - San Lorenzo CA, US
Jung Sheng Hoei - Fremont CA, US
Jason Guo - San Jose CA, US
William Saiki - Mountain View CA, US

Micron Technology, Inc. - Boise ID

G11C 11/34

36518522, 36518529, 36518518, 36518519

Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.

7843725, Nov 30, 2010

Jun 11, 2008

12/137171

Vishal Sarin - Cupertino CA, US
Jung-Sheng Hoei - Newark CA, US
Jonathan Pabustan - San Lorenzo CA, US
Frankie F. Roohparvar - Monte Sereno CA, US

Micron Technology, Inc. - Boise ID

G11C 16/04

36518503, 36518512, 36518518, 36518905

A memory device and programming and/or reading process is described that programs a row of non-volatile multi-level memory cells (MLC) in a single program operation to minimize disturb within the pages of the row, while verifying each memory cell page of the row separately. In one embodiment of the present invention, the memory device utilizes data latches to program M-bits of data into each cell of the row and then repurposes the data latches during the subsequent page verify operations to read M+L bits from each cell of the selected page at a higher threshold voltage resolution than required. In sensing, the increased threshold voltage resolution/granularity allows interpretations of the actual programmed state of the memory cell and enables more effective use of data encoding and decoding techniques such as convolutional codes where additional granularity of information is used to make soft decisions reducing the overall memory error rate.

7864589, Jan 4, 2011

Aug 14, 2008

12/191523

Vishal Sarin - Cupertino CA, US
Jonathan Pabustan - San Lorenzo CA, US
Frankie F. Roohparvar - Monte Sereno CA, US

Micron Technology, Inc. - Boise ID

G11C 16/04

36518521, 36518522

Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided. In one such method, a ramp voltage signal is generated by a digital count signal. A memory cell being program verified is turned on by a particular verify voltage of the ramp voltage signal in response to a digital count of the digital count signal. The memory cell turning on generates a bit line indication that causes the digital count to be compared to a representation of the target data to be programmed in the memory cell. The comparator circuit generates an indication when the digital count is greater than or equal to the target data.

7974136, Jul 5, 2011

Dec 22, 2009

12/645337

Geeng-Chuan Michael Chern - Cupertino CA, US
Ben Sheen - Milpitas CA, US
Jonathan Pabustan - San Lorenzo CA, US
Der-Tsyr Fan - Taiwan, TW
Yaw Wen Hu - Cupertino CA, US
Prateep Tuntasood - San Jose CA, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C 16/04

36518529, 36518517, 36518518, 36518519, 36518522

A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”).

8023334, Sep 20, 2011

Oct 31, 2008

12/262405

Jung-Sheng Hoei - Newark CA, US
Jonathan Pabustan - San Lorenzo CA, US
Vishal Sarin - Cupertino CA, US
William H. Radke - Los Gatos CA, US
Frankie F. Roohparvar - Monte Sereno CA, US

Micron Technology, Inc. - Boise ID

G11C 16/04

36518524, 365194

A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Memory cell signal line propagation delay compensation can be accomplished by characterizing the memory cell signal line propagation delay, such as determining an amount of error due to the delay, and pre-compensating the programmed threshold voltage of the memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Alternatively, memory cell signal line propagation delay can be post-compensated for, or the pre-compensation fine tuned, after sensing the threshold voltages of the selected memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Other methods, devices, etc. , are also disclosed.

8117375, Feb 14, 2012

Oct 17, 2007

11/873894

Vishal Sarin - Cupertino CA, US
Frankie F. Roohparvar - Monte Sereno CA, US
Jonathan Pabustan - San Lorenzo CA, US
Jung-Sheng Hoei - Fremont CA, US

Micron Technology, Inc. - Boise ID

G06F 12/00

711103, 711154, 36518512, 36518529

In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.