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Jon A Loschke

from Austin, TX
Age ~55
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Also known as:
John A Loschke
Phone and address:
6523 Lost Horizon Dr, Austin, TX 78759
(512) 372-3477
Related to:
Bruce L O'BrienDavid C Loschke, 80Kari A O'Brien, 52Barbara P Matheson, 78John A O'Brien, 49Melissa Watson, 42Shawnee A Yantorno, 68
Connected to:
Allan P Loschky, 72Melissa E Loschy, 40Justin M Losciale, 34Micah Losciale, 52Stephanie R Loscig, 51Richard U Loscutoff, 82Chad M Lose, 44Eric S Lose, 29Jay W Lose, 84Scott R Lose, 67

Jon Loschke Phones & Addresses

  • 6523 Lost Horizon Dr, Austin, TX 78759 (512) 372-3477
  • 11305 Oak Knoll Dr, Austin, TX 78759 (512) 918-3567
  • Gainesville, FL
  • Largo, FL
  • 6523 Lost Horizon Dr, Austin, TX 78759

Work

Company: Intrinsity Apr 2000 to Apr 2010 Position: Senior design engineer

Education

Degree: Master of Science, Masters School / High School: University of Florida 1988 to 1994 Specialities: Electrical Engineering

Industries

Semiconductors

Resumes

Resumes

Jon Loschke Photo 1

Jon Loschke

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Location:
11305 Oak Knoll Dr, Austin, TX 78759
Industry:
Semiconductors
Work:
Intrinsity Apr 2000 - Apr 2010
Senior Design Engineer
Apple Apr 2010 - Apr 2010
Gpu Design Manager
Motorola 1994 - 2000
Design Engineer
Education:
University of Florida 1988 - 1994
Master of Science, Masters, Electrical Engineering

Publications

Us Patents

System And Method For Speculative Global History Prediction Updating

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US Patent:
7707398, Apr 27, 2010
Filed:
Nov 13, 2007
Appl. No.:
11/985025
Inventors:
Timothy A. Olson - Austin TX, US
Terrence Matthew Potter - Austin TX, US
Jon A. Loschke - Austin TX, US
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
G06F 9/00
US Classification:
712240, 712239, 712234
Abstract:
A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.

Global History Branch Prediction Updating Responsive To Taken Branches

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US Patent:
7844806, Nov 30, 2010
Filed:
Jan 31, 2008
Appl. No.:
12/023303
Inventors:
Jon A. Loschke - Austin TX, US
Timothy A. Olson - Austin TX, US
Terrence Matthew Potter - Austin TX, US
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
G06F 9/38
US Classification:
712240
Abstract:
A system and method are provided for updating a global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts a microprocessor instruction of consecutive operations, including a conditional branch operation with an associated branch address, at a first stage in a pipelined microprocessor execution process. A global history record (GHR) of conditional branch resolutions and predictions is accessed and hashed with the branch address, creating a first hash result. The first hash result is used to access an indexed branch history table (BHT) of branch direction counts and the BHT is used to make a branch prediction. If the branch prediction being “taken”, the current GHR value is left-shifted and hashed with the branch address, creating a second hash result which is used in creating an updated GHR.

Microprocessor System For Simultaneously Accessing Multiple Branch History Table Entries Using A Single Port

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US Patent:
7849299, Dec 7, 2010
Filed:
May 5, 2008
Appl. No.:
12/115514
Inventors:
Terrence Matthew Potter - Austin TX, US
Jon A. Loschke - Austin TX, US
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00
US Classification:
712240
Abstract:
Provided is a means for accessing multiple entries from a branch history table (BHT) in a single clock cycle, in the context of pipelined instruction processing. In a first clock cycle, a plurality of conditional branch instructions is fetched. A value is accessed from a global history record (GHR) of conditional branch resolutions and predictions for a fetched conditional branch instruction. An associated instruction address is hashed with a left-shifted GHR value. The result is used to access a word in an indexed BHT stored in a single-port random access memory (RAM). The word comprises a branch direction count for the plurality of fetched conditional branch instructions. In a second clock cycle a conditional branch instruction is executed at an execute stage and the BHT is written with an updated branch direction count in response to a resolution of the executed conditional branch instruction.

System And Method For Repairing A Speculative Global History Record

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US Patent:
7904705, Mar 8, 2011
Filed:
Mar 11, 2010
Appl. No.:
12/722220
Inventors:
Timothy A. Olson - Austin TX, US
Terrence Matthew Potter - Austin TX, US
Jon A. Loschke - Austin TX, US
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
G06F 9/00
US Classification:
712240, 712239, 712234
Abstract:
A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.

Method For Repairing A Speculative Global History Record

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US Patent:
7975133, Jul 5, 2011
Filed:
Jan 29, 2011
Appl. No.:
13/016986
Inventors:
Timothy A. Olson - Austin TX, US
Terrence Matthew Potter - Austin TX, US
Jon A. Loschke - Austin TX, US
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
G06F 9/00
US Classification:
712240, 712239, 712234
Abstract:
A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.

Hybrid Adder Using Dynamic And Static Circuits

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US Patent:
20120311009, Dec 6, 2012
Filed:
May 2, 2012
Appl. No.:
13/462324
Inventors:
Ben D. Jarrett - Austin TX, US
Justin J. Friesenhahn - Austin TX, US
Jon A. Loschke - Austin TX, US
International Classification:
G06F 7/50
US Classification:
708700
Abstract:
A hybrid adder may include static partial sum circuits that operate to generate partial sums of operands, where each operand may be divided into groups that include multiple bits. A first subset of the static partial sum circuits may generate a partial sum of a corresponding group of the two or more operands assuming a carry in of 0 to the corresponding group, and a second subset may similarly assume a carry in of 1 to the corresponding group. The adder may further include a dynamic carry tree circuit that generates arithmetic carry signals, where each of the arithmetic carry signals corresponds to a respective group of sum bits. The adder may further include a multiplexer that, during operation, selects each of the groups of sum bits from either of the first or the second subsets of static partial sum circuits dependent upon corresponding ones of the arithmetic carry signals.

Apparatus And Method For Implementing A Content Addressable Memory Circuit With Two Stage Matching

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US Patent:
58931376, Apr 6, 1999
Filed:
Nov 29, 1996
Appl. No.:
8/753752
Inventors:
Charley Michael Parks - Austin TX
Jon Ashor Loschke - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 1200
US Classification:
711108
Abstract:
A circuit and method is provided for implementing a content addressable memory circuit (100) in which at least one output word is produced which corresponds to the content of a match word. A binary search logic circuit (103) binarily searches the memory array (101) to find a match entry with multiple words whose content is equal to that of an input value with multiple words. The amount of words in each match entry is user programmable and defined at startup. The CAM (100) is capable of masking out words to be compared or outputted and allows overlapping of words to be compared and outputted. Output signals indicate whether a match has been found.

Apparatus And Method For Concurrent Search Content Addressable Memory Circuit

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US Patent:
59563362, Sep 21, 1999
Filed:
Sep 27, 1996
Appl. No.:
8/722587
Inventors:
Jon Ashor Loschke - Austin TX
Charley Michael Parks - Austin TX
Mark Franklin - Austin TX
Kenneth Wade Jones - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H04L 1228
US Classification:
370392
Abstract:
A circuit and method is provided for implementing a content addressable memory circuit (100) in which an output word is produced which corresponds to the content of a reference word containing an ATM header. According to a first aspect, a binary search logic circuit (104) binarily searches the memory array (101) to find a match word whose content is equal to that of the reference word. Output signals indicate either that a match has been found or that the binary searching of the memory array (101) should continue at addresses either above or below the location address of the match word. According to a second aspect, the content addressable memory circuit (100) performs a concurrent search of switching identifiers, virtual circuit identifiers and virtual path identifiers, to determine if a virtual path connection or virtual circuit connection exists for an ATM header.
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Jon A Loschke from Austin, TX, age ~55 Get Report