John J Talvacchio

7830644, Nov 9, 2010

Mar 5, 2007

11/713783

Narsingh B. Singh - Ellicott City MD, US
John J. Talvacchio - Ellicott City MD, US
Marc Sherwin - Catonsville MD, US
Andre Berghmans - Owing Mills MD, US
David J. Knuteson - Columbia MD, US
David Kahler - Arbutus MD, US
Brian Wagner - Baltimore MD, US
John D. Adam - Millersville MD, US

Northop Grumman Systems Corporation - Los Angeles CA

H01G 4/06
H01G 4/005

361311, 361303

Methods of producing polycrystalline and single crystal dielectrics are disclosed, including dielectrics comprising CaCuTiOor LaGaSiO. Superior single crystals are manufactured with improved crystallinity by atomic lattice constant adjustments to the dielectric and to the substrate on which it is grown. Dielectric materials made according to the disclosed methods are useful for manufacture of energy storage devices, e. g. capacitors.

20070121274, May 31, 2007

Jul 12, 2006

11/484597

John Talvacchio - Ellicott City MD, US
James Murduck - Ellicott City MD, US
Gregory DeSalvo - Joppa MD, US
Rowland Clarke - Sykesville MD, US
Abigail Kirschenbaum - Baltimore MD, US
Deborah Partlow - Crownsville MD, US

H01G 4/06

361311000

Embodiments of the invention provide parallel plate capacitors comprising a bulk single crystal or single crystal film dielectric material disposed between the parallel plates and capacitors comprising one or more bulk single crystal or single crystal film dielectrics each disposed between two electrodes. Energy storage devices incorporating these capacitors also are disclosed.

20130119351, May 16, 2013

Nov 11, 2011

13/294473

Patrick B. Shea - Alexandria VA, US
Erica C. Folk - Linthicum Heights MD, US
Daniel J. Ewing - Kensington MD, US
John J. Talvacchio - Ellicott City MD, US

H01L 39/22

257 31, 438 2, 257E39014

Methods are provided of forming a Josephson junction (JJ) quantum bit (qubit). In one embodiment, the method comprises forming a JJ trilayer on a substrate. The JJ trilayer is comprised of a dielectric layer sandwiched between a bottom superconductor material layer and a top superconductor material layer. The method further comprises performing a thermal hardening process on the JJ trilayer to control diffusion of the dielectric layer into the bottom superconductor material layer and the top superconductor material layer, and etching openings in the JJ trilayer to form one or more JJ qubits.

20130157864, Jun 20, 2013

Dec 19, 2011

13/330270

John J. Talvacchio - Ellicott City MD, US
Erica C. Folk - Linthicum Heights MD, US
Sean R. McLaughlin - Severn MD, US
David J. Phillips - Richmond VA, US

H01L 27/18
H01L 39/24
H01L 39/02

505150, 505470, 505410, 427 62, 216 13, 257663

A integrated circuit and methods for fabricating the circuit are provided. The circuit integrates at least one circuit element formed from a material that is superconducting at temperatures less than one hundred milliKelvin and at least one resistor connected to the circuit element. The resistor is formed from an alloy of transition metals that is resistive at temperatures less than one hundred milliKelvin.

50844377, Jan 28, 1992

Feb 28, 1990

7/486474

John J. Talvacchio - Churchill PA

Westinghouse Electric Corp. - Pittsburgh PA

H01L 2144
H01L 3912

505 1

This is a method for making an ohmic connection between a semiconductor and oxide superconductor, the connection being such that current can pass between the semiconductor and the superconductor without going through a degraded portion which is greater than the coherence length of the superconductor. The method can comprise depositing a buffer layer (which is essentially inert to the oxide superconductor) on a first portion of a semiconductor substrate, and depositing oxide superconductor on the barrier layer, and depositing a superconductor contact layer (e. g. of gold or silver) on the oxide superconductor, and depositing a semiconductor contact layer on a second portion of the semiconductor substrate (the semiconductor contact layer being, for example, of aluminum, or a refractory metal silicide); and depositing a layr (e. g. of gold or aluminum) on the semiconductor contact layer and on at least a portion of the superconductor contact layer to electrically connect the semiconductor contact laye and the superconductor contact layer. Alternately, the method can comprise depositing a buffer layer on a first portion of a substrate, and depositing oxide superconductor on the barrier layer, and depositing a superconductor contact layer on the oxide superconductor, and depositing a semiconductor on a second portion of the substrate, and depositing a semiconductor contact layer on the semiconductor, and depositing a layer on the semiconductor contact layer and on at least a portion of the superconductor contact layer to electrically connect the semiconductor contact layer and the superconductor contact layer.

20140357493, Dec 4, 2014

Aug 15, 2014

14/460988

PATRICK B. SHEA - ALEXANDRIA VA, US
ERICA C. FOLK - LINTHICUM HEIGHTS MD, US
DANIEL J. EWING - OVERLAND PARK KS, US
JOHN J. TALVACCHIO - ELLICOTT CITY MD, US

NORTHROP GRUMMAN SYSTEMS CORPORATION - FALLS CHURCH VA

G06N 99/00
H01L 39/22
H01L 39/24

505170, 257 32

A Josephson junction (JJ) quantum bit (qubits) arranged on a substrate is provided. In one embodiment, each qubit comprises a dielectric layer, a superconductor base layer portion underlying the dielectric layer and a first dielectric diffused region adjacent a dielectric layer/superconductor base layer portion junction. The qubit further comprise a superconductor mesa layer portion overlying the dielectric layer and having a second dielectric diffused region adjacent a dielectric layer/superconductor mesa layer portion junction, the first and second dielectric diffused regions mitigating further diffusion from other semiconductor processes on the plurality of qubits.