Brett John Rolfson

6448133, Sep 10, 2002

Nov 20, 2000

09/717941

Randhir P. S. Thakur - Boise ID
Brett Rolfson - Boise ID

Micron Technology, Inc. - Boise ID

H01L 218242

438253, 438151, 438164, 438788, 438396

An embodiment of the present invention teaches a capacitor dielectric in a wafer cluster tool for semiconductor device fabrication formed by a method by the steps of: forming nitride adjacent a layer by rapid thermal nitridation; and subjecting the nitride to an ozone ambient, wherein the ozone ambient is selected from the group consisting of an ambient containing an the presence of ultraviolet light and ozone gas, an ambient containing ozone gas or an ambient containing an NF /ozone gas mixture.

6787482, Sep 7, 2004

Aug 14, 2002

10/223004

Randhir P. S. Thakur - Boise ID
Brett Rolfson - Boise ID

Micron Technology, Inc. - Boise ID

H01L 2131

438788, 438253, 438396, 438151

An embodiment of the present invention teaches a capacitor dielectric in a wafer cluster tool for semiconductor device fabrication formed by a method by the steps of: forming nitride adjacent a layer by rapid thermal nitridation; and subjecting the nitride to an ozone ambient, wherein the ozone ambient is selected from the group consisting of an ambient containing an ultraviolet/ozone mixture, an ambient containing an ozone or an ambient containing an NF /ozone mixture.

59665955, Oct 12, 1999

Nov 12, 1997

8/968382

Randhir P. S. Thakur - Boise ID
Brett Rolfson - Boise ID

Micron Technology, Inc. - Boise ID

H01L 2100
H01L 21324

438151

An embodiment of the present invention teaches a capacitor dielectric in a wafer cluster tool for semiconductor device fabrication formed by a method by the steps of: forming nitride adjacent a layer by rapid thermal nitridation; and subjecting the nitride to an ozone ambient, wherein the ozone ambient is selected from the group consisting of an ambient containing the presence of ultraviolet light and ozone gas, an ambient containing ozone gas or an ambient containing an NF. sub. 3 /ozone gas mixture.

57168628, Feb 10, 1998

Jun 16, 1995

8/491179

Aftab Ahmad - Boise ID
Randhir P. S. Thakur - Boise ID
Kirk Prall - Boise ID
Tyler Lowrey - Boise ID
Brett Rolfson - Boise ID

Micron Technology, Inc. - Boise ID

H01L 21265
H01L 2102
H01L 2170
H01L 2700

437 41

This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are formed from a single conductive layer (typically a doped polysilicon layer) using separate masking steps. In one embodiment of the present invention teaches a semiconductor manufacturing process for forming p-channel devices by the steps of: defining p-channel transistor gate electrodes having substantially vertical sidewalls over n-well regions; performing a p-type impurity implant into the n-well regions to form p-channel source and drain terminals on opposing sides of each the p-channel transistor gate electrodes; performing an angled n-type impurity implant into the n-well regions to form an n-type halo around the p-channel source and drain terminals; performing a low temperature oxidation step at a temperature ranging between 600. degree. -957. degree. C. , to form poly gate sidewall oxidation about the vertical sidewalls of the p-channel transistor gate electrodes; and performing a p-type impurity implant into the n-well regions.

52815005, Jan 25, 1994

Sep 4, 1991

7/754893

David A. Cathey - Boise ID
Brett Rolfson - Boise ID

Micron Technology, Inc. - Boise ID

G03F 900

430 5

A method of preventing null formation is performed on a phase shifted photomask including a clear quartz substrate, dark chrome feature features, and alternating clear phase shifters raised from the substrate. The phase shifter features are terminated in a transmissive, optically clear edge. To prevent null formation and consequent formation of stringers on the surface of the integrated circuit, the substantially vertical edge of the optically clear end of the phase shifter is tapered. The slope at any point along the tapered edge between the photomask substrate and the phase shifter is set to an angle, typically less than forty-five degrees, shallow enough that the point spread function does not produce an image. The point spread function of the imaging system spreads out the null, which is therefore not printed into the photoresist layer on the integrated circuit. The tapered edge of the phase shifter is created by either discrete or continuous etching methods.

6162666, Dec 19, 2000

Aug 4, 1999

9/368481

Randhir P. S. Thakur - Boise ID
Brett Rolfson - Boise ID

Micron Technology, Inc - Boise ID

H01L 2100
H01L 218242
H01L 2120
H01L 2131
H01L 21469

438164

An embodiment of the present invention teaches a capacitor dielectric in a wafer cluster tool for semiconductor device fabrication formed by a method by the steps of: forming nitride adjacent a layer by rapid thermal nitridation; and subjecting the nitride to an ozone ambient, wherein the ozone ambient is selected from the group consisting of an ambient containing an the presence of ultraviolet light and ozone gas, an ambient containing an ozone gas or an ambient containing an NF. sub. 3 /ozone gas mixture.