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John R Providenza

from Beaverton, OR
Age ~70
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Also known as:
John Robert Providenza, John P Providenza, John R Providenz, Providenza John
Phone and address:
13600 SW Weir Rd, Beaverton, OR 97008
(503) 524-8260
Related to:
Claude M Providenza, 42Valerie Providenza, 39Bonnie L Providenza, 68
Connected to:
Althea Providence, 40Ayanna C Providence, 29Cynthia Y Providence, 56Jean S Providence, 56Joseph T Providence, 73Arnold B Provido, 53Rowena S Provido, 42Rockchel Provillon, 51Barbara L Provin, 73Chris A Province, 65

John Providenza Phones & Addresses

  • 13600 SW Weir Rd, Beaverton, OR 97008 (503) 524-8260
  • San Rafael, CA
  • Watsonville, CA
  • 5470 2Nd St, Tillamook, OR 97141 (503) 815-1538
  • Santa Cruz, CA

Resumes

Resumes

John Providenza Photo 1

John Providenza

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Location:
Portland, Oregon Area
Industry:
Computer Hardware
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John Providenza

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Publications

Us Patents

Shared Resource Arbitration Method And Apparatus

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US Patent:
6678774, Jan 13, 2004
Filed:
Dec 16, 1999
Appl. No.:
09/464248
Inventors:
John R. Providenza - Beaverton OR
Assignee:
Koninklijke Philips Electronics N.V. - Eindhoven
International Classification:
G06F 1300
US Classification:
710240, 710 14, 710 22, 710 28, 710 40, 710107, 710111, 710310
Abstract:
An arbiter apparatus for selecting an agent to use a shared resource such as memory. A normal round robin list is utilized in the selection process during boot operation. During the initialization process, a dynamic list is generated in accordance with system requirements. The dynamic list selection process may take any of several forms. In a first mode, it may select only priority listed agents, any one of which may be repeated during a given cycle of selection. In a second mode, it may select a designated buddy agent when the selected priority agent is idle. In either mode, and in accordance with a set of priority selection rules, one or more lowest priority default agents may be given access when the designated higher priority agents for a given list entry slot are idle.

Image Processor Memory For Expediting Memory Operations

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US Patent:
54870518, Jan 23, 1996
Filed:
Mar 18, 1994
Appl. No.:
8/210355
Inventors:
John R. Providenza - Beaverton OR
Lee Boekelheide - Tigard OR
Assignee:
Network Computing Devices, Inc. - Mountain View CA
International Classification:
G11C 1300
US Classification:
365233
Abstract:
An electronic data storage memory performs logic operations on the data values existing in its storage cells to eliminate the number of necessary memory accesses during bitblts. The time in which a bitblt can be completed in an image processing system is prolonged because of the number of memory cycles performed during a "raster operation". Thus, to reduce the number of necessary memory cycles, simple logic operations are performed in image processor memory so that a raster operation may take place without having to read, for example, the destination operand from memory. Since a bitblt performs a raster operation on each pixel in the bitblt block, the reduction in memory access time is proportional to the size of the bitblt block.

Bit Aligned Data Block Transfer Method And Apparatus

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US Patent:
53476310, Sep 13, 1994
Filed:
Oct 12, 1993
Appl. No.:
8/135797
Inventors:
John R. Providenza - Beaverton OR
Lee Boekelheide - Tigard OR
Assignee:
Network Computing Devices, Inc. - Mountain View CA
International Classification:
G06F 1562
US Classification:
395164
Abstract:
The number of required clock periods in a bit aligned block transfer operation may be reduced by analyzing the logical relationship between source, destination and pattern operands prior to fetching these operands from memory. If the result of the raster operation can be determined without actually using the value of any of the operands, the result is provided without reading memory values. When the raster operation will have no effect on the existing destination operand, the write operation is also canceled.

Event Counting Prescaler

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US Patent:
48499242, Jul 18, 1989
Filed:
Jun 13, 1985
Appl. No.:
6/744581
Inventors:
John R. Providenza - Beaverton OR
Bruce Ableidinger - Beaverton OR
Assignee:
Tektronix, Inc. - Beaverton OR
International Classification:
G06F 750
US Classification:
364770
Abstract:
An apparatus for counting occurrences of a plurality of events characterized by unique event numbers includes a random access memory for storing event count numbers at addresses corresponding to the event numbers. The memory is addressed by an event number as the associated event occurs, and the event count number stored at such address is read and latched to an input of an adder. The adder increments the latched event count number and the incremented event count number is then written back into the memory at the current event number address. A buffer is provided to store the current event number whenever the adder overflows as a result of a count. Several such event numbers may be stored in the buffer for subsequent retrieval by an external controller thereby permitting the controller to determine when an event has been counted a fixed number of times and to increment its own internally stored count at a slower rate than the rate at which data is applied to the prescaler.

Bit Aligned Data Block Transfer Method And Apparatus

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US Patent:
53135768, May 17, 1994
Filed:
Nov 23, 1990
Appl. No.:
7/617198
Inventors:
John R. Providenza - Beaverton OR
Lee Boekelheide - Tigard OR
Assignee:
Network Computing Devices, Inc. - Mountain View CA
International Classification:
G06F 1562
US Classification:
395164
Abstract:
The number of required clock periods in a bit aligned block transfer operation may be reduced by analyzing the logical relationship between source, destination and pattern operands prior to fetching these operands from memory. If the result of the raster operation can be determined without actually using the value of any of the operands, the result is provided without reading memory values. When the raster operation will have no effect on the existing destination operand, the write operation is also canceled.

Image Processor Memory For Expediting Memory Operations

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US Patent:
53455550, Sep 6, 1994
Filed:
Jun 14, 1993
Appl. No.:
8/077705
Inventors:
John R. Providenza - Beaverton OR
Lee Boekelheide - Tigard OR
Assignee:
Network Computing Devices, Inc. - Mountain View CA
International Classification:
G06F 1562
US Classification:
395164
Abstract:
An electronic data storage memory performs logic operations on the data values existing in its storage cells to eliminate the number of necessary memory accesses during bitblts. The time in which a bitblt can be completed in an image processing system is prolonged because of the number of memory cycles performed during a "raster operation". Thus, to reduce the number of necessary memory cycles, simple logic operations are performed in image processor memory so that a raster operation may take place without having to read, for example, the destination operand from memory. Since a bitblt performs a raster operation on each pixel in the bitblt block, the reduction in memory access time is proportional to the size of the bitblt block.

Optical Mandrel, Optical-Fiber Assembly Including An Optical Mandrel, And System For Detecting An Acoustic Signal Incident On An Optical-Fiber Assembly

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US Patent:
20200092661, Mar 19, 2020
Filed:
Sep 6, 2019
Appl. No.:
16/563578
Inventors:
- Polson MT, US
Peter S. Lovely - Portland OR, US
James Alexander Philp - Missoula MT, US
John R. Providenza - Beaverton OR, US
Timothy N. Roberts - Tigard OR, US
Leon J. Stevens - Polson MT, US
Philip J. Stimac - Montpelier VT, US
Assignee:
Adelos, Inc. - Polson MT
International Classification:
H04R 23/00
G01H 9/00
Abstract:
An embodiment of a system includes a light source, an optical assembly, and an electronic circuit. The light source (e.g., a laser) is configured to generate a source optical signal. The optical assembly is configured to direct the source optical signal into an end of an optical-fiber assembly that includes an optical fiber having a section wrapped multiple turns around a mandrel and including mandrel zones, and to receive, from the end of the optical-fiber assembly, a return optical signal. The electronic circuit is configured to select at least one mandrel zone in response to a component of the return optical signal from the at least one mandrel zone, and to detect an acoustic signal incident on the mandrel in response to the component of the return optical signal.

Noise Management For Optical Time Delay Interferometry

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US Patent:
20170284895, Oct 5, 2017
Filed:
Aug 27, 2015
Appl. No.:
14/837592
Inventors:
- Polson MT, US
Stephen Timothy Doll - Big Arm MT, US
James Alexander Philp - Missoula MT, US
John R. Providenza - Beaverton OR, US
Trinitie Marie Vance - Bainbridge Island WA, US
International Classification:
G01M 11/00
G01B 9/02
Abstract:
An integrated fiber interferometry interrogator for generating superimposed waves is disclosed. The system is optimized for efficiency and vibration attenuation. The system comprises an optical light source for generating a first signal, a first signal splitter which splits the first signal into a reference signal and an interrogation signal, optical modulators for modulating the signals, a fiber coupler connected to a fiber under test, an isolator, a circulator with a plurality of connections for directing the signals, a signal mixer for mixing the signals into superimposed waves, and photo diodes for receiving the superimposed waves.
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John R Providenza from Beaverton, OR, age ~70 Get Report