Resumes
Resumes
John Polstra Phones & Addresses
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1585 Channel Rd, Lopez Island, WA 98261 (360) 468-2269
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9346 California Ave, Seattle, WA 98136 (206) 932-6481 (206) 932-6482
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Bellevue, WA
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Palo Alto, CA
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Kent, OH
Business Records
Name / Title
Company / Classification
Phones & Addresses
Principal
John D Polstra Co Inc
Engineering Services · Engineering Services, Nsk · Nonclassifiable Establishments
Engineering Services · Engineering Services, Nsk · Nonclassifiable Establishments
1585 Channel Rd, Port Stanley, WA 98261
President,Secretary,Chairman ,Director
JOHN D POLSTRA & CO., INC
1585 Channel Rd, Lopez Island, WA 98261
Publications
Us Patents
Automatic Verification Of Kernel Circuitry Based On Analysis Of Memory Accesses
View pageUS Patent:
49892070, Jan 29, 1991
Filed:
Nov 23, 1988
Appl. No.:
7/275183
Inventors:
John D. Polstra - Seattle WA
Assignee:
John Fluke Mfg. Co., Inc. - Everett WA
International Classification:
G01R 3128
G06F 1100
G06F 1100
US Classification:
371 162
Abstract:
A method and apparatus for providing automatic verification of the kernel circuitry of a microprocessor-based system in which the microprocessor (. mu. P) include an instruction prefetch feature. During testing by memory emulation, the memory addresses accessed by the. mu. P are evaluated as to type of access, address and data size in accordance with a test program and a corresponding checking table to determine if such accesses are consistent with a funtional. mu. P of the same type. Other data structures such as flags and pointers are provided to enhance the verification operation and use of the checking table.
Kernel Testing Interface And Method For Automating Diagnostics Of Microprocessor-Based Systems
View pageUS Patent:
51365901, Aug 4, 1992
Filed:
Nov 24, 1989
Appl. No.:
7/441093
Inventors:
John D. Polstra - Seattle WA
Marshall H. Scott - Woodinville WA
Bruce T. White - Woodinville WA
Marshall H. Scott - Woodinville WA
Bruce T. White - Woodinville WA
Assignee:
John Fluke Mfg. Co., Inc. - Everett WA
International Classification:
G06F 1100
G01R 3128
G01R 3128
US Classification:
371 162
Abstract:
An improved testing apparatus and method for testing the kernel of a microprocessor based unit under test (UUT) in which connection to the UUT is made at both the memory connection socket and at the microprocessor with the microprocessor being in place and active in the UUT. The apparatus and method permits substantially full diagnostics of the kernel to be carried out in a systematic and automated manner in which the requirement of manual probing of the UUT is minimized. Connections at the microprocessor permit the development of high resolution sync signals for verification and evaluation of test results. The testing protocol implemented in the method includes the use of testing primitives which permit the development of a signature for each address and data bus line for the identification of the type as well as the location of any faults discovered by the apparatus. The method of testing exploits bootstrapping techniques including three primitives for bus test, data stimulus and address stimulus to optimize simultaneous testing and circuit fault diagnosis.
Computer Assisted Fault Isolation In Circuit Board Testing
View pageUS Patent:
47093668, Nov 24, 1987
Filed:
Jul 29, 1985
Appl. No.:
6/761027
Inventors:
Marshall H. Scott - Woodinville WA
John D. Polstra - Seattle WA
John D. Polstra - Seattle WA
Assignee:
John Fluke Mfg. Co., Inc. - Everett WA
International Classification:
G01R 3128
US Classification:
371 20
Abstract:
Circuit faults in an electronic system are isolated by a programmed computer that guides a technician node-by-node on a unit under test (UUT), such as a circuit board, to the source of a failure. Stimulus pattern signals are applied to the circuit, and responses at the circuit nodes are made by a measurement probe under the hand of the technician. As each node is probed, a stimulus pattern signal tailored for testing that node is applied to the UUT. The measured response is compared to a predetermined response corresponding to an operational UUT to generate a failure accusation or recommend the next node to be probed. The computer is programmed to expedite the search for the source of the failure by displaying to the technician clues which define the circuit nodes most apt to be defective as a result of preliminary functional testing of the UUT. The computer is further programmed to have a form of "intuition" whereby the particular nodes recommended for probing are determined in part by prior testing of the same type of UUT.
Memory Emulation Method And System For Testing And Troubleshooting Microprocessor-Based Electronic Systems
View pageUS Patent:
48688223, Sep 19, 1989
Filed:
Feb 19, 1988
Appl. No.:
7/158223
Inventors:
Marshall H. Scott - Woodinville WA
Robert E. Cuckler - Bothell WA
John D. Polstra - Seattle WA
Anthony R. Vannelli - Everett WA
W. Douglas Hazelton - Everett WA
Robert E. Cuckler - Bothell WA
John D. Polstra - Seattle WA
Anthony R. Vannelli - Everett WA
W. Douglas Hazelton - Everett WA
Assignee:
John Fluke Mfg. Co., Inc. - Everett WA
International Classification:
G06F 1100
G01R 3128
G01R 3128
US Classification:
371 16
Abstract:
A method and system for testing and troubleshooting microprocessor-based electronic systems employs memory emulation techniques as well as other techniques to provide complete functionality tests and fault location. Fine-resolution sync pulses may be generated at preselected time positions during a bus cycle of interest to facilitate full troubleshooting fault isolation. Other features include bus testing using memory emulation techniques, using the chip select line of ROMs to encode test results, and techniques that keep a target microprocessor functioning in a system in which the kernel is dead.
Apparatus, Method And Data Structure For Validation Of Kernel Data Bus
View pageUS Patent:
49583476, Sep 18, 1990
Filed:
Nov 23, 1988
Appl. No.:
7/275185
Inventors:
Bruce T. White - Woodinville WA
John D. Polstra - Seattle WA
Craig V. Johnson - Everett WA
John D. Polstra - Seattle WA
Craig V. Johnson - Everett WA
Assignee:
John Fluke Mfg. Co., Inc. - Everett WA
International Classification:
G01R 3128
US Classification:
371 295
Abstract:
An apparatus, method and data structure for validating the data bus of a microprocessor-based unit under test in which bit patterns having half as many bits as the width of the data bus are applied to the data bus along with another bit pattern which is either the complemented or true replication of the bit pattern. Evaluation of the resulting bit patterns on the data bus permits a validation of the entire width of the data bus which, if no faults are reported, obviates not only probing of the data bus by the operator but data bus diagnosis, as well. A particular data structure of a preferred bit pattern sequence avoids any fault on any data line being reported as a pass.