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John A Ostop

from Greensburg, PA
Deceased
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Related to:
Joseph Resnick JriDianne E Ostop, 74Joseph ResnickChris J Resnick, 44Dennis J ResnickAnne M Resnick
Connected to:
Jenine J Ostopick, 39Valerie A Ostopoff, 57Alcione N Ostorga, 71Julio E Ostorga, 49Catherine E Ostos, 67Diana P Ostos, 56Jessica Ostos, 31Josue M Ostos, 44Vicente V Ostos, 60Karissa I Ostoski, 43

John Ostop Phones & Addresses

  • 425 Glenmeade Rd, Greensburg, PA 15601 (724) 216-5578
  • Lutherville Timonium, MD
  • 204 Ambleside Dr, Severna Park, MD 21146 (410) 647-1482
  • Acme, PA
  • Jeannette, PA
  • Baltimore, MD

Work

Company: Northrop grumman corporation Nov 1987 to Jul 2006 Position: Retired

Education

Degree: Bachelors School / High School: Carnegie Mellon University 1964 to 1968 Specialities: Electronics Engineering, Electronics

Industries

Defense & Space

Resumes

Resumes

John Ostop Photo 1

John Ostop

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Location:
Greensburg, PA
Industry:
Defense & Space
Work:
Northrop Grumman Corporation Nov 1987 - Jul 2006
Retired
Westinghouse Electric Company Nov 1969 - Nov 1987
Engineer
Education:
Carnegie Mellon University 1964 - 1968
Bachelors, Electronics Engineering, Electronics

Publications

Us Patents

High Power, High Frequency Bipolar Transistor With Alloyed Gold Electrodes

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US Patent:
39355870, Jan 27, 1976
Filed:
Aug 14, 1974
Appl. No.:
5/497349
Inventors:
John A. Ostop - Greensburg PA
Paul M. Kisinko - Greensburg PA
Joseph F. Henry - Palatine IL
Assignee:
Westinghouse Electric Corporation - Pittsburgh PA
International Classification:
H01L 2972
H01L 29167
H01L 29207
H01L 29227
US Classification:
357 34
Abstract:
A bipolar transistor is provided with both high voltage and high frequency capabilities. A semiconductor body of a resistivity between 10 and 100 ohm-cm forms the collector region of the transistor and has an epitaxial semiconductor layer grown on a major surface thereof of a resistivity between about 0. 5 and 10 ohm-cm and of a thickness between about 20 and 100 microns and of a conductivity type opposite from the body. At least one emitter region and integral emitter electrode are alloyed into the epitaxial layer preferably in annular rings. A base region is formed in the epitaxial layer between the emitter and semiconductor body and around the emitter region, said base region having a minimum thickness between the emitter region and the semiconductor body in the interior of the body of less than 20 and preferably between 5 and 10 microns. Base electrodes are alloyed into the epitaxial layer preferably spaced from the emitter region and emitter electrode preferably in concentric annular rings and a center circular member.

Microchannel Cooling Of High Power Semiconductor Devices

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US Patent:
58014420, Sep 1, 1998
Filed:
Jul 22, 1996
Appl. No.:
8/681207
Inventors:
Robin E. Hamilton - Millersville MD
Paul G. Kennedy - Grasonville MD
John Ostop - Severna Park MD
Martin L. Baker - Sykesville MD
Gregory A. Arlow - Eldersburg MD
John C. Golombeck - Gambrills MD
Thomas J Fagan - Pittsburgh PA
Assignee:
Northrop Grumman Corporation - Los Angeles CA
International Classification:
H01L 2334
US Classification:
257714
Abstract:
Cooling of densely packaged semiconductor devices is achieved by microchannels which extract heat by forced convection and the use of fluid coolant located as close as possible to the heat source. The microchannels maximize heat sink surface area and provides improved heat transfer coefficients, thereby allowing a higher power density of semiconductor devices without increasing junction temperature or decreasing reliability. In its preferred embodiment, a plurality of microchannels are formed directly in the substrate portion of a silicon or silicon carbide chip or die mounted on a ground plane element of a circuit board and where a liquid coolant is fed to and from the microchannels through the ground plane. The microchannels comprise a plurality of closed-ended slots or grooves of generally rectangular cross section. Fabrication methods include deposition and etching, lift-off processing, micromachining and laser cutting techniques.

Method Of Making A Self Protected Thyristor

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US Patent:
45148988, May 7, 1985
Filed:
Feb 18, 1983
Appl. No.:
6/468016
Inventors:
John X. Przybysz - Penn Hills PA
John A. Ostop - Youngwood PA
Assignee:
Westinghouse Electric Corp. - Pittsburgh PA
International Classification:
H01L 21223
H01L 21302
H01L 2974
US Classification:
29582
Abstract:
The present invention is directed to a thyristor self-protected against overvoltage by the avalanche mechanism, the protection resulting from a laser scribed ring shaped groove cut in the top surface of the thyristor and extending into one base region of the thyristor whereby the forward blocking junction is contoured toward the reverse blocking junction under the ring shaped groove, and to the process for making the thyristor.

Technique For Making Asymmetric Thyristors

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US Patent:
42643830, Apr 28, 1981
Filed:
Aug 23, 1979
Appl. No.:
6/069195
Inventors:
John A. Ostop - Jeannette PA
Robert W. Marks - Mt. Pleasant PA
Assignee:
Westinghouse Electric Corp. - Pittsburgh PA
International Classification:
H01L 21225
US Classification:
148188
Abstract:
A method for doping a wafer of n-type seimiconductor material having two surfaces includes the steps of applying a boron solution to a first surface of the wafer and heating the wafer to drive the boron into the semiconductor wafer for forming a first p-type region. Both surfaces of the wafer are then exposed to a gallium vapor for forming a second p-type region on the second surface and deepening the extent of the first p-type region.

Glass-Sealed Power Thyristor

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US Patent:
43297072, May 11, 1982
Filed:
Jul 16, 1980
Appl. No.:
6/169249
Inventors:
David L. Moore - Jeannette PA
John A. Ostop - Jeannette PA
Joseph E. Johnson - Pittsburgh PA
Assignee:
Westinghouse Electric Corp. - Pittsburgh PA
International Classification:
H01L 2330
H01L 2348
H01L 2944
US Classification:
357 73
Abstract:
A glass disc-shaped thyristor is disclosed. The thyristor comprises a body of semiconductive material having a first emitter region, a first base region, a second base region and a second emitter region therein. A cathode electrode and a gate electrode are affixed to one major surface, and an anode electrode is affixed to the second major surface of the body of semiconductor material. The cathode electrode is disc-shaped and is concentrically positioned with respect to the annular-shaped gate electrode. A ring-shaped glass member is affixed to a first major surface of the body of semiconductive material and to the edges of the cathode and base electrodes to form a seal protecting a PN junction at the interface of the first emitter and base regions. An anode electrode is affixed to the second major surface of the body of semiconductive material. A second annular shaped glass member is affixed to the edge of the body of semiconductive material to form a seal protecting PN junctions formed at the interface of the first and second base regions and at the interface of the second base region with the second emitter region.

Die Attached Process For Sic

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US Patent:
58518525, Dec 22, 1998
Filed:
Feb 13, 1996
Appl. No.:
8/600777
Inventors:
John A. Ostop - Severna Park MD
Li-Shu Chen - Ellicott City MD
Assignee:
Northrop Grumman Corporation - Los Angeles CA
International Classification:
H01L 2158
US Classification:
438106
Abstract:
A die attach procedure for SiC uses the scrubbing technique to bond a SiC die to a package. A first layer is formed on the SiC die. This first layer, preferably of nickel, bonds to the SiC die. A second layer, preferably amorphous silicon, is then formed on the first layer. The second layer bonds to the first layer, and forms a eutectic with the material, usually gold, plating the package when the SiC die is scrubbed onto the package.

Glass Sealed Diode

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US Patent:
41617460, Jul 17, 1979
Filed:
Mar 28, 1978
Appl. No.:
5/891090
Inventors:
Joseph E. Johnson - Churchill PA
John A. Ostop - Greensburg PA
David L. Moore - Jeannette PA
Assignee:
Westinghouse Electric Corp. - Pittsburgh PA
International Classification:
H01L 2302
US Classification:
357 73
Abstract:
A glass sealed semiconductor diode is disclosed. The diode includes a fusion which comprises a body of semiconductor material having a PN junction therein and metal electrodes affixed to opposed major surfaces of the semiconductor body. The fusion is encircled by an annular-shaped glass member with an inner surface of the annular-shaped glass member fused to an edge surface of the fusion to form a protective layer over the PN junction. An annular metallic member encircles the annular glass member with an inner surface thereof fused to an outer surface of the annular glass member.

Method Of Making A Transistor Device

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US Patent:
40408779, Aug 9, 1977
Filed:
Aug 24, 1976
Appl. No.:
5/717076
Inventors:
Joseph E. Johnson - Churchill PA
John A. Ostop - Greensburg PA
Assignee:
Westinghouse Electric Corporation - Pittsburgh PA
International Classification:
H01L 2122
US Classification:
148187
Abstract:
A plurality of discrete transistor devices are produced on a semiconductor wafer and isolated from one another by moat etching. A passivation layer is then deposited in the moats separating the discrete transistor devices. The semiconductor wafer is then scribed and broken along lines delineated by the moats. The disclosed method permits testing of each discrete transistor device prior to separation from the wafer.
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John A Ostop from Greensburg, PADeceased Get Report