John Hong Lin

7123877, Oct 17, 2006

Nov 8, 2001

10/007435

John Lin - Downey CA, US

Broadcom Corporation - Irvine CA

H04B 7/00
H04Q 7/20

455 412, 455507, 455514, 455517

A baseband controller includes a microsequencer that is formed to include special hardware resources and a configuration that facilitates using the micro-sequencer as a real-time baseband controller. The microsequencer includes a 72-bit correlator that way also be used as an accumulator. The correlator is able to communicate with a 72-bit arithmetic logic unit, enabling the correlator to act as an accumulator, as well as a plurality of clocks and timers that facilitate the timing functionality to satisfy Bluetooth specifications. More specifically, the microsequencer includes at least four clocks and eight times. The four clocks include an externally driven Bluetooth clock, an externally driven real-time clock, a native Bluetooth clock and a native real-time clock. The microsequencer further includes at least four registers for temporarily storing computational data. The storage registers have different sizes for storing different sized packets of computational data.

7151745, Dec 19, 2006

Nov 8, 2001

10/008873

John Lin - Downey CA, US
Paris Chen - Walnut CA, US

Broadcom Corporation - Irvine CA

H04J 1/16
H04J 3/14

370230, 370235

A baseband controller system creates and maintains a schedule of synchronized events and reviews the schedule as a part of determining whether to initiate a transmission of a non-synchronous event. One aspect is to avoid a possibility of collision between synchronized and non-synchronized communication events. The schedule of synchronized events are evaluated in relation to the present time and determine whether a non-synchronized event may be transmitted without the likelihood of a collision. The transmission determination includes evaluating future time periods to see if a synchronized event is scheduled during a time period in which the non-synchronized event would continue to be transmitted for those non-synchronized events that span two or more defined time periods in length.

7583932, Sep 1, 2009

Oct 9, 2006

11/539783

John Lin - Downey CA, US

Broadcom Corporation - Irvine CA

H04B 7/00

455 412, 455 413, 455507, 455514, 455517

A baseband controller includes a microsequencer with special hardware resources circuitry and a configuration that supports real-time Bluetooth functionality for an upper limit of Bluetooth slave devices. The microsequencer includes a 72-bit correlator that may also be used as an accumulator, wherein the topology provides that the correlator can communicate with a 72-bit arithmetic logic unit that correspondingly enables the correlator to act as an accumulator. The microsequencer also includes a plurality of clocks and timers for facilitating Bluetooth timing functionality, and at least four registers for temporarily storing computational data, where each of the storage registers have different sizes for accommodating different-sized packets of computational data.

7756100, Jul 13, 2010

Dec 18, 2006

11/612468

John Lin - Downey CA, US
Paris Chen - Walnut CA, US

Broadcom Corporation - Irvine CA

H04B 7/212

370347, 3703954, 370468, 370346, 4554521

A baseband controller system creates and maintains a schedule of synchronized events and reviews the schedule as a part of determining whether to initiate a transmission of a non-synchronous event (one that is not time sensitive, for example, e-mail). One aspect of the present invention is to create a system and method that avoids a possibility of collision between synchronized and non-synchronized communication events. A synchronized event is a scheduled transmission of time sensitive data such as what is often known as continuous bit rate data. Examples include video and voice wherein a collision (inability to transmit the continuous bit rate data) may result in degradation of signal quality at the receiving end. The inventive system and method evaluate the schedule of synchronized events in relation to the present time and determine whether a non-synchronized event may be transmitted without the likelihood of a collision. Making the determination that such a transmission may occur includes evaluating future time periods to see if a synchronized event is scheduled during a time period in which the non-synchronized event would continue to be transmitted for those non-synchronized events that span two or more defined time periods in length.

7929935, Apr 19, 2011

Jun 2, 2008

12/131676

John H. Lin - Downey CA, US
Sherman Lee - Rancho Palso Verde CA, US
Vivian Y. Chou - Alhambra CA, US

Broadcom Corporation - Irvine CA

H04B 1/06

455259, 375372, 711100

A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

7974578, Jul 5, 2011

Aug 31, 2009

12/551359

John Lin - Downey CA, US

Broadcom Corporation - Irvine CA

H04B 7/00

455 412, 455 413, 455507, 455514, 455517

A baseband controller includes a microsequencer with special hardware resources circuitry and a configuration that supports real-time micronetwork functionality for an upper limit of slave devices. The microsequencer includes a correlator that may also be used as an accumulator, wherein the topology provides that the correlator can communicate with an arithmetic logic unit that correspondingly enables the correlator to act as an accumulator. The microsequencer also includes a plurality of clocks and timers for facilitating micronetwork timing functionality, and at registers for temporarily storing computational data, where each of the storage registers have different sizes for accommodating different-sized packets of computational data.

8196869, Jun 12, 2012

Dec 29, 2011

13/340333

Bernard Friedrich Kutter - Centennial CO, US
Frank Charles Zegler - Centennial CO, US
Cliff E. Willey - Frederica DE, US
John K. Lin - Frederica DE, US
Mohamed M. Ragab - Centennial CO, US
Michael W. Dew - Centennial CO, US

United Launch Alliance, LLC - Englewood CO

B64G 1/52
B64G 1/58
B64G 1/00

2441717, 2441723, 2441725, 2441581

A cryogenic propellant depot and sunshield are provided for operation in earth orbit to fuel or refuel other space vehicles. The sunshield is deployed to effectively mitigate solar radiation emanating from the earth and the sun thereby providing a long term storage solution for cryogenic fluids prone to boil-off. The depot has supporting subsystems to include station keeping equipment and communication equipment so that the depot can be independently controlled. Inflatable booms are used to deploy the sunshield in a desired pattern around the depot.

20030086485, May 8, 2003

Nov 8, 2001

10/008872

John Lin - Downey CA, US
Vivian Chou - Torrance CA, US

H04B001/38
H04L005/16

375/219000

A baseband controller system includes a master to a multi-slave asynchronous transmit FIFO structure that enables the traffic to all slaves to be independent of each other in a manner that reduces the shortcomings of traditional FIFO structures. The inventive FIFO structure includes a plurality of pointer blocks wherein each of the FIFO pointer blocks comprises a plurality of one-byte pointers that point to command blocks. The command blocks, in turn, define an address that point to a starting address of a data block. Accordingly, because the FIFO pointer blocks only include an address for a pointer to a command block instead of the actual data that is to be transmitted, the size of the FIFO structure is dramatically reduced. Thus, the transmission order for the data blocks is determined by ordering the pointers instead of by ordering the data itself.