John D Edmondson

20200401541, Dec 24, 2020

Jul 6, 2020

16/921795

- Santa Clara CA, US
Ronny KRASHINSKY - San Francisco CA, US
Steven HEINRICH - Madison AL, US
Shirish GADRE - Fremont CA, US
John EDMONDSON - Arlington MA, US
Jack CHOQUETTE - Palo Alto CA, US
Mark GEBHART - Round Rock TX, US
Ramesh JANDHYALA - Austin TX, US
Poornachandra RAO - Cedar Park TX, US
Omkar PARANJAPE - Austin TX, US
Michael SIU - Santa Clara CA, US

G06F 13/28
G06F 12/0891
G06F 12/0811
G06F 12/084
G06F 12/0895
G06F 12/122

A unified cache subsystem includes a data memory configured as both a shared memory and a local cache memory. The unified cache subsystem processes different types of memory transactions using different data pathways. To process memory transactions that target shared memory, the unified cache subsystem includes a direct pathway to the data memory. To process memory transactions that do not target shared memory, the unified cache subsystem includes a tag processing pipeline configured to identify cache hits and cache misses. When the tag processing pipeline identifies a cache hit for a given memory transaction, the transaction is rerouted to the direct pathway to data memory. When the tag processing pipeline identifies a cache miss for a given memory transaction, the transaction is pushed into a first-in first-out (FIFO) until miss data is returned from external memory. The tag processing pipeline is also configured to process texture-oriented memory transactions.

20180322077, Nov 8, 2018

May 4, 2017

15/587213

- Santa Clara CA, US
Ronny KRASHINSKY - San Francisco CA, US
Steven HEINRICH - Madison AL, US
Shirish GADRE - Fremont CA, US
John EDMONDSON - Arlington MA, US
Jack CHOQUETTE - Palo Alto CA, US
Mark GEBHART - Round Rock TX, US
Ramesh JANDHYALA - Austin TX, US
Poornachandra RAO - Cedar Park TX, US
Omkar PARANJAPE - Austin TX, US
Michael SIU - Santa Clara CA, US

G06F 13/28
G06F 12/0891
G06F 12/0811
G06F 12/084

A unified cache subsystem includes a data memory configured as both a shared memory and a local cache memory. The unified cache subsystem processes different types of memory transactions using different data pathways. To process memory transactions that target shared memory, the unified cache subsystem includes a direct pathway to the data memory. To process memory transactions that do not target shared memory, the unified cache subsystem includes a tag processing pipeline configured to identify cache hits and cache misses. When the tag processing pipeline identifies a cache hit for a given memory transaction, the transaction is rerouted to the direct pathway to data memory. When the tag processing pipeline identifies a cache miss for a given memory transaction, the transaction is pushed into a first-in first-out (FIFO) until miss data is returned from external memory. The tag processing pipeline is also configured to process texture-oriented memory transactions.

20180322078, Nov 8, 2018

Sep 26, 2017

15/716461

- Santa Clara CA, US
Ronny KRASHINSKY - San Francisco CA, US
Steven HEINRICH - Madison AL, US
Shirish GADRE - Fremont CA, US
John EDMONDSON - Arlington MA, US
Jack CHOQUETTE - Palo Alto CA, US
Mark GEBHART - Round Rock TX, US
Ramesh JANDHYALA - Austin TX, US
Poornachandra RAO - Cedar Park TX, US
Omkar PARANJAPE - Austin TX, US
Michael SIU - Santa Clara CA, US

G06F 13/28
G06F 12/0811
G06F 12/0891
G06F 12/084

A unified cache subsystem includes a data memory configured as both a shared memory and a local cache memory. The unified cache subsystem processes different types of memory transactions using different data pathways. To process memory transactions that target shared memory, the unified cache subsystem includes a direct pathway to the data memory. To process memory transactions that do not target shared memory, the unified cache subsystem includes a tag processing pipeline configured to identify cache hits and cache misses. When the tag processing pipeline identifies a cache hit for a given memory transaction, the transaction is rerouted to the direct pathway to data memory. When the tag processing pipeline identifies a cache miss for a given memory transaction, the transaction is pushed into a first-in first-out (FIFO) until miss data is returned from external memory. The tag processing pipeline is also configured to process texture-oriented memory transactions.

20150089198, Mar 26, 2015

Sep 20, 2013

14/033378

- Santa Clara CA, US
Peter NELSON - San Francisco CA, US
Aniket NAIK - Sunnyvale CA, US
John H. EDMONDSON - Arlington MA, US

NVIDIA CORPORATION - Santa Clara CA

G06F 9/38
G06F 9/30

712214

An issue control unit is configured to control the rate at which an instruction issue unit issues instructions to an execution pipeline in order to avoid spikes in power drawn by that execution pipeline. The issue control unit maintains a history buffer that reflects, for N previous cycles, the number of instructions issued during each of those N cycles. If the total number of instructions issued during the N previous cycles exceeds a threshold value, then the issue control unit throttles the instruction issue unit from issuing instructions during a subsequent cycle. In addition, the issue control unit increases the threshold value in proportion to the number of previously issued instructions and based on a variety of configurable parameters. Accordingly, the issue control unit maintains granular control over the rate with which the instruction issue unit “ramps up” to a maximum instruction issue rate.