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John Charles Andolina

from Vista, CA
Age ~55
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Also known as:
John C Andolina, John Charles Ardoling, Charles Andolina
Phone and address:
2501 Longmont Rd, Vista, CA 92084
Related to:
Claire Andolina, 24Jimi E Carpenter, 53Charles R Andolina, 91Shannon M Andolina, 53Michael B Beatty, 40Tiffaney A Carpenter, 54
Connected to:
Brian J Andolina, 50Charles J Andolina, 60Christina G Andolino, 46Craig N Andolina, 72Cynthia M Andolina, 62Frank Andolina, 58James W Andolina, 68Joan P Andolina, 73John S Andolina, 81Kathy G Andolina, 67

John Andolina Phones & Addresses

  • 2501 Longmont Rd, Vista, CA 92084
  • 1981 Pinewood Rd, Vista, CA 92083
  • Carlsbad, CA
  • Charlotte, NC
  • Troy, NY
  • San Diego, CA
  • New Hampton, NY

Professional Records

Medicine Doctors

John Andolina Photo 1

John R. Andolina

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Specialties:
Internal Medicine
Work:
Clinton Medical Associates
2400 Clinton Ave S FL 2, Rochester, NY 14618
(585) 341-7685 (phone), (585) 341-4220 (fax)
Education:
Medical School
Georgetown University School of Medicine
Graduated: 1976
Procedures:
Electrocardiogram (EKG or ECG)
Vaccine Administration
Conditions:
Acne
Acute Bronchitis
Acute Pharyngitis
Acute Sinusitis
Acute Upper Respiratory Tract Infections
Languages:
English
Spanish
Description:
Dr. Andolina graduated from the Georgetown University School of Medicine in 1976. He works in Rochester, NY and specializes in Internal Medicine. Dr. Andolina is affiliated with Strong Memorial Hospital.

Business Records

Name / Title
Company / Classification
Phones & Addresses
John Andolina
Administration
Albany Port Employers Assn Inc
Pension/Health/Welfare Fund
106 Smith Blvd, Albany, NY 12202
(518) 462-0591

Publications

Us Patents

Trusted Boot

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US Patent:
8166289, Apr 24, 2012
Filed:
Feb 5, 2009
Appl. No.:
12/366602
Inventors:
John R. Owens - Carlsbad CA, US
John C. Andolina - Vista CA, US
Stuart Shanken - San Diego CA, US
Richard L. Quintana - Carlsbad CA, US
Assignee:
ViaSat, Inc. - Carlsbad CA
International Classification:
G06F 9/00
H04L 29/06
H04N 7/16
US Classification:
713 2, 713153, 726 26
Abstract:
In one embodiment, a method for trusted booting of a cryptographic processor system is disclosed. Default image(s) is loaded into a field-programmable logic chip or circuit (FPLC). The default image(s) cannot perform cryptographic processing, but can perform a first algorithm that is unclassified. A processor, internal or external to the FPLC, can be used with the default image. A multi-layer or multi-part key has portions stored in two different places. A protected image is decrypted with the multi-layer key using the first algorithm and loaded into the FPLC. Cryptographic processing is performed using a second algorithm classified by the government.

Input Output Access Controller

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US Patent:
8312292, Nov 13, 2012
Filed:
Jul 31, 2008
Appl. No.:
12/184079
Inventors:
John R. Owens - Carlsbad CA, US
John C. Andolina - Vista CA, US
Stuart N. Shanken - San Diego CA, US
Richard L. Quintana - Carlsbad CA, US
Assignee:
ViaSat, Inc. - Carlsbad CA
International Classification:
G06F 21/00
G06F 13/00
G06F 13/28
G06F 15/173
H04L 29/06
US Classification:
713189, 726 1, 711100, 711163, 709223, 709224, 709225, 709226
Abstract:
A device for high-assurance processing is disclosed. A processing circuit uses an access controller to assure that the processing circuit operates properly. The processing circuit runs software programs and is programmable. The access controller is programmable, but not programmable by the processing circuit. Peripherals or segments of the address space of the processing circuit is regulated. In a particular state, the peripherals that are available are regulated by the access controller. In some embodiments, the transition from state-to-state can also be regulated by the access controller.

Trusted Labeler

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US Patent:
8392983, Mar 5, 2013
Filed:
Jul 31, 2008
Appl. No.:
12/184048
Inventors:
Richard L. Quintana - Carlsbad CA, US
John R. Owens - Carlsbad CA, US
John C. Andolina - Vista CA, US
Stuart N. Shanken - San Diego CA, US
Assignee:
ViaSat, Inc. - Carlsbad CA
International Classification:
H04L 29/00
H04L 12/28
H04L 12/56
US Classification:
726 13, 726 12, 370389
Abstract:
A cryptographic device and method are disclosed for processing different levels of classified information. Input and output ports are physically isolated on the cryptographic device. Within the cryptographic device, each port has its packets labeled in such a way that it can be processed differently from other packets by a cryptographic module. High-assurance techniques are used to assure labeling and proper processing of the packets. These labeled packets are intermixed on common pathways regardless of level of classification. Despite intermixing, separation of the packets is assured through the process.

Trusted Cryptographic Switch

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US Patent:
20070245413, Oct 18, 2007
Filed:
Jul 3, 2006
Appl. No.:
11/428520
Inventors:
John Andolina - Vista CA, US
Dennis Bourget - Carlsbad CA, US
Assignee:
ViaSat, Inc. - Carlsbad CA
International Classification:
G06F 15/16
US Classification:
726011000
Abstract:
A cryptographic switch for routing information is disclosed. The cryptographic switch includes a first and second input ports, a first and second output ports and a first and second cryptographic paths. The first cryptographic path is configured to programmably couple between at least one of the first or second input ports and at least one of the first or second output ports. The second cryptographic path is configured to programmably couple between at least one of the first or second input ports and at least one of the first or second output ports.

Multi-Level Key Manager

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US Patent:
20090034734, Feb 5, 2009
Filed:
Jul 31, 2008
Appl. No.:
12/184062
Inventors:
John R. Owens - Carlsbad CA, US
John C. Andolina - Vista CA, US
Stuart N. Shanken - San Diego CA, US
Richard L. Quintana - Carlsbad CA, US
Assignee:
ViaSat, Inc. - Carlsbad CA
International Classification:
H04L 9/14
US Classification:
380277
Abstract:
A cryptographic device and method are disclosed for processing different levels of classified information. A memory caches keys for use in a cryptographic processor. The cryptographic processor requests a key associated with a particular classification level when processing a packet of the particular classification level. The cryptographic device confirms that the key and the packet are of the same classification level in a high-assurance manner. Checking header information of the keys one or more times is performed in one embodiment. Some embodiments authenticate the stored key in a high-assurance manner prior to providing the key to the cryptographic device.

Overlapping State Areas For Programmable Crypto Processing Circuits

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US Patent:
20090235064, Sep 17, 2009
Filed:
Feb 5, 2009
Appl. No.:
12/366619
Inventors:
John R. Owens - Carlsbad CA, US
John C. Andolina - Vista CA, US
Stuart Shanken - San Diego CA, US
Richard L. Quintana - Carlsbad CA, US
Assignee:
ViaSat, Inc. - Carlsbad CA
International Classification:
G06F 9/00
US Classification:
713100
Abstract:
In one embodiment, a method for operating a field-programmable logic chip or circuit (FPLC) is disclosed. Operation of the FPLC includes a configuration state and a cryptographic processing state. Switching between states is controlled by a state machine. Each state has one or more images. Transferring between states causes some or all images from the other state being overwritten.

System Security Manager

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US Patent:
20090240951, Sep 24, 2009
Filed:
Feb 5, 2009
Appl. No.:
12/366600
Inventors:
John R. Owens - Carlsbad CA, US
John C. Andolina - Vista CA, US
Stuart Shanken - San Diego CA, US
Richard L. Quintana - Carlsbad CA, US
Assignee:
ViaSat, Inc. - Carlsbad CA
International Classification:
H04L 9/06
G06F 11/00
US Classification:
713189, 714 48, 714E11002
Abstract:
In another embodiment, a method for securing a field-programmable logic chip or circuit (FPLC) is disclosed. Information is cryptographically processed within the FPLC. An error condition is detected outside of the FPLC and the error condition is communicated to the FPLC to disrupt an image(s) within the FPLC. Optionally, at least a portion of a key can be erased such that cryptographic processing is curtailed or eliminated.

Hardware-Based Cryptographic Accelerator

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US Patent:
20100011047, Jan 14, 2010
Filed:
Jul 7, 2009
Appl. No.:
12/499006
Inventors:
David Jackson - Escondido CA, US
John Andolina - Vista CA, US
Assignee:
ViaSat, Inc. - Carlsbad CA
International Classification:
G06F 7/52
G06F 7/50
H04L 9/00
US Classification:
708491, 380277, 708620, 708670, 380 28
Abstract:
A system, method, and apparatus for performing hardware-based cryptographic operations are disclosed. The apparatus can include an encryption device with a hardware accelerator having an accumulator, a multiplier circuit, an adder circuit, and a state machine. The state machine can control successive operation of the hardware accelerator to carry out a rapid, multiplier-based reduction of a large integer by a prime modulus value. Optionally, the hardware accelerator can include a programmable logic device such as a field-programmable gate array with one or more dedicated multiple-accumulate blocks.
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John Charles Andolina from Vista, CA, age ~55 Get Report