Search

Joel A Auernheimer

from Chandler, AZ
Age ~47
Get Report
Also known as:
Joel Arthur Auernheimer, Joel N Auernheimer, Joel A Aurnheimer, Joel A Auenheimer
Phone and address:
4553 W Detroit St, Chandler, AZ 85226
Related to:
Judy C Auernheimer, 72Rebecca L Fortune, 64Sunny Auernheimer, 70Clara Lochridge, 43David Auernheimer, 48
Connected to:
Kira R Auernheimer, 34Brad J Auernig, 46James P Auers, 67John F Auers, 40Theodora V Auersperg, 62Lalani D Auerswald, 35Chrissa J Auestad, 35Jeremy K Auestad, 45Alfred W Aufdemberge, 75

Joel Auernheimer Phones & Addresses

  • 4553 W Detroit St, Chandler, AZ 85226
  • Gilbert, AZ
  • 4120 Pinchot Ave, Phoenix, AZ 85018
  • Tempe, AZ
  • Maricopa, AZ
  • 1920 E Maryland Ave UNIT 21, Phoenix, AZ 85016

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Resumes

Resumes

Joel Auernheimer Photo 1

Software Platform Applications Engineer

View page
Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
Intel Corporation since Jan 2011
Software Platform Applications Engineer
Intel Corporation Jan 2001 - Jan 2011
Analog Engineer
Mayo Clinic May 1996 - Aug 2000
Engineering Co-op
Arizona State University Aug 1996 - May 2000
Research Associate
Education:
Arizona State University 2007 - 2013
Master of Science (MS), Computer Science Arizona State University 1995 - 2000
Master of Science (MS), Electrical Engineering
Skills:
Programming
Product Development
Signal Integrity
Embedded Systems
Engineering
Debugging
Semiconductors
Analog
Simulations
Joel Auernheimer Photo 2

Joel Auernheimer

View page

Business Records

Name / Title
Company / Classification
Phones & Addresses
Joel A Auernheimer
Manager
GTD REALTY, LLC
4939 W Ray Rd #4-335, Chandler, AZ 85226

Publications

Us Patents

Forming A Substrate Core With Embedded Capacitor And Structures Formed Thereby

View page
US Patent:
7224571, May 29, 2007
Filed:
Sep 2, 2005
Appl. No.:
11/218357
Inventors:
Sriram Srinivasan - Chander AZ, US
John S. Guzek - Chandler AZ, US
Cengiz A. Palanduz - Chandler AZ, US
Victor Prokofiev - Phoenix AZ, US
Joel A. Auernheimer - Phoenix AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01G 4/228
US Classification:
3613063, 361311, 361313, 3613061, 3613211, 3613214
Abstract:
Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a substrate core by attaching a first dielectric layer to a second conductive layer of a thin film capacitor, and attaching a second dielectric layer to a first conductive layer of the thin film capacitor.

Flex Tape Architecture For Integrated Circuit Signal Ingress/Egress

View page
US Patent:
7321167, Jan 22, 2008
Filed:
Jun 4, 2003
Appl. No.:
10/455906
Inventors:
Dong Zhong - Chandler AZ, US
Yuan-Liang Li - Chandler AZ, US
Jung Kang - Chandler AZ, US
Prashant Parmar - Gilbert AZ, US
Hyunjun Kim - Chandler AZ, US
Joel Auernheimer - Phoenix AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/495
US Classification:
257701, 257664, 257668, 257E23177
Abstract:
In an integrated circuit design, flex tape is used to provide signal ingress/egress to/from the integrated circuit design. Various architectures for the signal ingress/egress via flex tape is provided. In one embodiment, coaxial design is provided. In another embodiment, a coplanar waveguide design is provided.

Array Capacitor For Decoupling Multiple Voltage Rails

View page
US Patent:
7355836, Apr 8, 2008
Filed:
Jun 7, 2005
Appl. No.:
11/146587
Inventors:
Kaladhar Radhakrishnan - Chandler AZ, US
Nicholas L Holmberg - Gilbert AZ, US
Joel A Auernheimer - Phoenix AZ, US
Dustin P Wood - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01G 4/228
US Classification:
3613062, 3613061, 3613063, 3613211, 361311, 361313
Abstract:
An array capacitor is provided. The array capacitor includes a plurality of ground planes inside a dielectric substrate, and a plurality of ground vias. The ground vias electrically connect the ground planes together. Further, the ground vias are connected to ground terminals of the array capacitor to enable electrical coupling between the ground planes and the ground terminals. The array capacitor further includes a plurality of power planes inside the dielectric substrate. The power planes and the ground planes are arranged alternatively inside the dielectric substrate. Each power plane comprises a plurality of power-plane-sections which are mutually electrically isolated. The array capacitor also includes a plurality of power vias which electrically connect the power planes together. Further, the power vias are connected to power terminals of the array capacitor to enable electrical coupling between the power planes and power terminals.

Array Capacitor With Resistive Structure

View page
US Patent:
7365428, Apr 29, 2008
Filed:
Oct 22, 2004
Appl. No.:
10/971379
Inventors:
Joel A. Auernheimer - Phoenix AZ, US
Nicholas L. Holmberg - Gilbert AZ, US
Kaladhar Radhakrishnan - Chandler AZ, US
Dustin P. Wood - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/34
H01L 23/495
H01L 27/06
H01L 27/07
H01L 21/50
H01L 21/48
H01L 21/44
US Classification:
257724, 257723, 257E27025, 257E27045, 257E23057
Abstract:
An apparatus comprises a first plurality of contacts disposed on a first side of the apparatus, adapted to engage with a first corresponding plurality of contacts on an external integrated circuit package. The apparatus further comprises a plurality of capacitive storage structures selectively coupled to the first plurality of contacts, one or more traces, and a second plurality of contacts disposed on the first side. The second plurality of contacts are adapted to engage with a second corresponding plurality of contacts on the external integrated circuit package, wherein at least two of the second plurality of contacts are adapted to be coupled to at least a first trace of the one or more traces to form a first resistive structure.

Array Capacitors For Broadband Decoupling Applications

View page
US Patent:
7495336, Feb 24, 2009
Filed:
Dec 30, 2005
Appl. No.:
11/322384
Inventors:
Joel A. Auernheimer - Phoenix AZ, US
Nicholas Holmberg - Gilbert AZ, US
Kaladhar Radhakrishnan - Chandler AZ, US
Dustin P. Wood - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/00
US Classification:
257758, 257E23057, 257532, 257924, 257528, 257728, 257724, 257725
Abstract:
An integrated broadband array capacitor includes at least two regions with varying capacitance and response times. The broadband array capacitor is disposable on a socket or is integral with a socket. A method of operating the broadband array capacitor includes responding to load transients from each of the at least two regions. A computing system is also disclosed that includes the broadband array capacitor.

Land Grid Array With Socket Plate

View page
US Patent:
20060046527, Mar 2, 2006
Filed:
Aug 25, 2004
Appl. No.:
10/925451
Inventors:
Brent Stone - Chandler AZ, US
Joel Auernheimer - Phoenix AZ, US
International Classification:
H01R 12/00
US Classification:
439066000
Abstract:
A grounded conductive plate in a land grid array package assembly includes a plurality of openings. The openings allow contacts from the socket to pass through to contact a package. The diameter of each opening is customizable to produce desired impedance between the contacts and the conductive plate. Impedance discontinuity seen by signals passing through the socket may be reduced.

Forming A Substrate Core With Embedded Capacitor And Structures Formed Thereby

View page
US Patent:
20060143886, Jul 6, 2006
Filed:
Dec 30, 2004
Appl. No.:
11/027386
Inventors:
Sriram Srinivasan - Chandler AZ, US
John Guzek - Chandler AZ, US
Cengiz Palanduz - Chandler AZ, US
Victor Prokofiev - Phoenix AZ, US
Joel Auernheimer - Phoenix AZ, US
International Classification:
H01G 7/00
H01G 4/20
US Classification:
029025410, 361312000, 029846000
Abstract:
Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a substrate core by attaching a first dielectric layer to a second conductive layer of a thin film capacitor, and attaching a second dielectric layer to a first conductive layer of the thin film capacitor.

Forming A Substrate Core With Embedded Capacitor And Structures Formed Thereby

View page
US Patent:
20060143887, Jul 6, 2006
Filed:
Oct 26, 2005
Appl. No.:
11/260023
Inventors:
Sriram Srinivasan - Chander AZ, US
John Guzek - Chandler AZ, US
Cengiz Palanduz - Chandler AZ, US
Victor Prokofiev - Phoenix AZ, US
Joel Auernheimer - Phoenix AZ, US
International Classification:
H01G 7/00
H01R 9/00
H01G 4/06
US Classification:
029025410, 029842000, 029852000, 361313000
Abstract:
Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a substrate core by attaching a first dielectric layer to a second conductive layer of a thin film capacitor, and attaching a second dielectric layer to a first conductive layer of the thin film capacitor.
Control profile
Joel A Auernheimer from Chandler, AZ, age ~47 Get Report