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Joachim C Rayos

from Austin, TX
Age ~68
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Also known as:
Joachim H Rayos
Phone and address:
3103 Yellowpine Ter, Austin, TX 78757
Related to:
Dulce Maria Sanchez, 40Epifanio N Morales, 59Eleno Aguirre, 59Clarita Delacruz, 67Adam Contreras, 55Yuliana GuevaraMiguel Rayos, 58
Connected to:
Andrew P Rayos, 67Arturo Rayos, 88Ashley R Rayos, 33Efren A Rayos, 28Floro H Rayos, 91Gabriel Rayos, 40Jaime A Rayos, 55Krysela Rayos, 31Marco A Rayos, 27Mike Rayos, 59

Joachim Rayos Phones & Addresses

  • 3103 Yellowpine Ter, Austin, TX 78757

Resumes

Resumes

Joachim Rayos Photo 1

Material Technology Engineer

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Samsung Austin Semiconductor
Material Technology Engineer
Freescale Semiconductor 2000 - 2012
Package Engineer - Global Assembly Operations
Amkor Technology 1998 - 2000
Bga Technical Development - Process Engineer
Education:
De La Salle University 1989
Skills:
Quality Management
Technology
Engineering Management
Supply Chain Optimization
Ic Packaging
Materials Science
Supply Chain Engineering
Assembly Language
Electronics Packaging
Electronics
Asic
Supply Chain Management
Substrates
Jmp
Materials
Product Engineering
Engineering
Cmos
Semiconductor Industry
Cross Functional Team Leadership
Change Management
Manufacturing
Change Programmes
Soc
Design of Experiments
Microelectronics
Failure Analysis
Management
Semiconductors
Project Management
Supplier Risk Management
Process Engineering
Spc
R&D
Process Simulation
Silicon
Ic
Joachim Rayos Photo 2

Process Engineer At Freescale Semiconductor, Inc.

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Position:
Process Engineer at Freescale Semiconductor, Inc.
Location:
Austin, Texas Area
Industry:
Semiconductors
Work:
Freescale Semiconductor, Inc.
Process Engineer

Publications

Us Patents

Method For Making An Interconnect Pad

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US Patent:
20050245059, Nov 3, 2005
Filed:
Apr 30, 2004
Appl. No.:
10/836152
Inventors:
Yuan Yuan - Austin TX, US
Burton Carpenter - Austin TX, US
Joachim Rayos - Austin TX, US
International Classification:
H01L021/44
US Classification:
438612000
Abstract:
An interconnect pad is made to have a convex shape which is a shape that has been found to useful in improving the reliability of solder joints. A seed pillar is formed by plating over a metal layer. This seed pillar is smaller than the intended size of the interconnect pad. After formation of this small seed pillar, a plating step is performed over the pillar that forms the desired convex shape for the interconnect pad.
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Joachim C Rayos from Austin, TX, age ~68 Get Report