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Jitendra K Swarnkar

from Fremont, CA
Age ~48
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Also known as:
Jitendra K Swaraka, Jitendra R
Phone and address:
41215 Joyce Ave, Fremont, CA 94539
Connected to:
Marcee G Swarny, 54Brandy J Swaro, 45David M Swaro, 58Charu Swaroop, 44Krishna R Swaroop, 32Mukesh Swaroop, 52Namit Swaroop, 50Neha Swaroop, 31Satinder Swaroop, 81Donna S Swarr, 69

Jitendra Swarnkar Phones & Addresses

  • 41215 Joyce Ave, Fremont, CA 94539
  • 1814 Bell Rd, Phoenix, AZ 85022
  • Sunnyvale, CA
  • San Jose, CA
  • San Diego, CA
  • Alameda, CA

Publications

Us Patents

Automated Scan Testing Of Ddr Sdram

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US Patent:
7793175, Sep 7, 2010
Filed:
Jan 10, 2008
Appl. No.:
11/972567
Inventors:
Jitendra Swarnkar - San Jose CA, US
Vincent Wong - Fremont CA, US
Jie Du - Santa Clara CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G11C 29/00
US Classification:
714718
Abstract:
A controller for scan testing a memory. The controller includes a control state machine for controlling the scan process, a test sequence stored in a random access memory used by the control state machine for controlling an actual memory test, a pattern generation data unit responsive to the control state machine for generating a test pattern that is written to and read from a memory under test, a configuration register read by the control state machine for configuring the controller and a fault location register written to by the control state machine for storing locations of defects in the memory. The controller is used to auto scan a memory in real time, interleaved with other processes accessing the memory. The controller has several modes of operation including operating in a periodic burst mode to conserve power and in a background mode so as not to interfere with other processes accessing the scanned memory.

Ddr Control

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US Patent:
7849345, Dec 7, 2010
Filed:
Oct 26, 2007
Appl. No.:
11/925605
Inventors:
Jitendra Kumar Swarnkar - San Jose CA, US
Jie Du - Santa Clara CA, US
Vincent Wong - Fremont CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 13/14
G06F 15/78
US Classification:
713401, 713400, 711105, 711158, 36523004, 36523008, 36523313, 710244
Abstract:
A computer system for writing data to a memory is disclosed. The memory controller in the computer system comprises a system clock, which is generated by the memory controller. A first register captures the lower data word based on the rising edge of the system clock. A second register, coupled to the first register, captures the output of the first register based on the rising edge of the system clock. A third register, captures the upper data word based on the falling edge of the system clock. A forth register, coupled to the third register, captures the output of the third register based on the falling edge of the system clock. A first multiplexer is coupled to a forth register and a second register. A delay element, coupled to the system clock and a first multiplexer, adjusts the phase of the system clock. A second multiplexer, coupled to the system clock, generates a data strobe.

Buffer Management System And Method

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US Patent:
7930450, Apr 19, 2011
Filed:
Jul 6, 2010
Appl. No.:
12/831061
Inventors:
Jitendra Kumar Swarnkar - San Jose CA, US
Jie Du - Santa Clara CA, US
Vincent Wong - Fremont CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 3/00
G11B 5/09
US Classification:
710 52, 360 51
Abstract:
The transfer of data from a host computer to a recordable disk in a disk drive operating on the host computer is managed. A buffer for temporarily storing data to be transferred between the host computer and the recordable disk is maintained, wherein the buffer comprises a plurality of host segments and a plurality of disk segments, and wherein each of the host segments and disk segments have a sector count value associated therewith. In a case where the transfer of data corresponds to a host segment, the host segment is selected from the plurality of host segments in the buffer. In a case where the transfer of data corresponds to a disk segment, the disk segment is selected from the plurality of disk segments in the buffer. In a case where a host segment is selected, the sector count value of the selected host segment is adjusted. In a case where a disk segment is selected, the sector count value of the selected disk segment is adjusted.

Automated Scan Testing Of Ddr Sdram

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US Patent:
7971111, Jun 28, 2011
Filed:
Sep 7, 2010
Appl. No.:
12/876654
Inventors:
Jitendra Kumar Swarnkar - San Jose CA, US
Vincent Wong - Fremont CA, US
Jie Du - Santa Clara CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G11C 29/00
US Classification:
714718
Abstract:
A controller for scan testing a memory. The controller includes a control state machine for controlling the scan process, a test sequence stored in a random access memory used by the control state machine for controlling an actual memory test, a pattern generation data unit responsive to the control state machine for generating a test pattern that is written to and read from a memory under test, a configuration register read by the control state machine for configuring the controller and a fault location register written to by the control state machine for storing locations of defects in the memory. The controller is used to auto scan a memory in real time, interleaved with other processes accessing the memory. The controller has several modes of operation including operating in a periodic burst mode to conserve power and in a background mode so as not to interfere with other processes accessing the scanned memory.

Unlimited Sub-Segment Support In A Buffer Manager

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US Patent:
8127100, Feb 28, 2012
Filed:
Apr 16, 2008
Appl. No.:
12/104357
Inventors:
Jitendra Kumar Swarnkar - Sunnyvale CA, US
Vincent Wong - Fremont CA, US
Jing Booth - San Jose CA, US
Jie Du - Santa Clara CA, US
Assignee:
Marvell International Ltd
International Classification:
G06F 12/00
G06F 13/00
G06F 13/28
G06F 9/26
G06F 9/34
US Classification:
711170, 711118, 711205
Abstract:
A system and method of buffer management may employ a common data structure that is recognizable by both hardware and firmware. In some implementations, hardware register settings may be programmed independent of firmware updates to an internal sub-segment description table maintained in an ASIC or other buffer manager logic. Implementation of such a common data structure in external memory may substantially reduce hardware real estate and complexity of a buffer manager ASIC by minimizing the number of required registers and eliminating the need for an internal sub-segment descriptor table. In addition, by eliminating the internal sub-segment descriptor table and allowing buffer manager logic to recognize a common data structure in external memory, the number of buffer sub-segments recognized by the buffer manager may be readily expanded, and may be limited only by the size of the external memory.

Sequential-Access Of Storage Media

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US Patent:
8503275, Aug 6, 2013
Filed:
Apr 20, 2012
Appl. No.:
13/452418
Inventors:
Jitendra Kumar Swarnkar - Fremont CA, US
Vincent Wong - Fremont CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G11B 5/09
US Classification:
369 5315, 369 5317, 369 5324, 369 4714, 360 53
Abstract:
The present disclosure describes apparatuses and techniques of improved sequential-access of storage media. In some aspects an indication that a media disk interface failed to read a sector of a sequential-read during a revolution of the media disk is received and the media disk interface is caused to attempt to read a next sector of the sequential-read subsequent the sector failed to be read during a same revolution of the media disk.

Automated Scan Testing Of A System-On-Chip (Soc)

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US Patent:
8522090, Aug 27, 2013
Filed:
May 24, 2011
Appl. No.:
13/114981
Inventors:
Jitendra Kumar Swarnkar - Sunnyvale CA, US
Vincent Wong - Fremont CA, US
Yun-Ho Wu - Milpitas CA, US
Rakeshkumar K. Patel - Sunnyvale CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G11C 29/00
US Classification:
714718
Abstract:
A method of testing a double data rate (DDR) memory interface within a System-on-chip (SoC). The method comprises generating a data stream within the SoC and writing the data stream to an internal memory within the SoC via the DDR memory interface. The method further comprises reading the data stream from the internal memory within the SoC and comparing the data stream generated within the SoC with the data stream read from the internal memory within the SoC.

Buffer Management System And Method

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US Patent:
7752356, Jul 6, 2010
Filed:
Oct 23, 2007
Appl. No.:
11/877410
Inventors:
Jitendra Kumar Swarnkar - San Jose CA, US
Jie Du - Santa Clarita CA, US
Vincent Wong - Fremont CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 3/00
G11B 5/09
US Classification:
710 52, 360 51
Abstract:
The transfer of data from a host computer to a recordable disk in a disk drive operating on the host computer is managed. A buffer for temporarily storing data to be transferred between the host computer and the recordable disk is maintained, wherein the buffer comprises a plurality of host segments and a plurality of disk segments, and wherein each of the host segments and disk segments have a sector count value associated therewith. In a case where the transfer of data corresponds to a host segment, the host segment is selected from the plurality of host segments in the buffer. In a case where the transfer of data corresponds to a disk segment, the disk segment is selected from the plurality of disk segments in the buffer. In a case where a host segment is selected, the sector count value of the selected host segment is adjusted. In a case where a disk segment is selected, the sector count value of the selected disk segment is adjusted.
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Jitendra K Swarnkar from Fremont, CA, age ~48 Get Report