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Jingyu Jenny Lian

from Hopewell Junction, NY
Age ~66
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Also known as:
Jingyu Y Lian, Jingyu J Lian, Jenny Lian, Jing Yu Lian, Jing Y Lian, Lian Jingyu
Phone and address:
24 Logans Way, East Fishkill, NY 12533
Related to:
Shelly Lian, 76
Connected to:
Amy S Lian, 59Anthony Lian, 40Bawi B Lian, 41Cherry H Lian, 44Cheryl A Lian, 66Corey K Lian, 36David M Lian, 74Emily A Lian, 35Feifei Lian, 35Freddy Lian, 57

Jingyu Lian Phones & Addresses

  • 24 Logans Way, Hopewell Jct, NY 12533
  • Hopewell Junction, NY
  • Fishkill, NY
  • Wallkill, NY
  • State College, PA

Work

Company: Globalfoundries Jul 2015 Position: Principle member of technical stuff -- design enablement

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Kyoto University Specialities: Philosophy

Skills

Sram • Semiconductors • Drc • Lvs • Testing • Eda • Ic • Cmos • Asic • Vlsi • Simulations • Semiconductor Industry • Characterization • Design of Experiments • Static Timing Analysis • Thin Films • Semiconductor Process • Standard Cell • Physical Design • R&D • Research and Development

Languages

English • Japanese • Mandarin

Industries

Information Technology And Services

Resumes

Resumes

Jingyu Lian Photo 1

Principle Member Of Technical Stuff -- Design Enablement

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Location:
Hopewell Junction, NY
Industry:
Information Technology And Services
Work:
Globalfoundries
Principle Member of Technical Stuff -- Design Enablement
Ibm
Senior Engineer -- Design Technology Inerfation
Intel Corporation Feb 2011 - Sep 2011
Senior Staff Engineer
Infineon Technologies Apr 1999 - Feb 2011
Senior Staff Engineer
Siemens Nov 1997 - Apr 1999
Senior Engineer
Education:
Kyoto University
Doctorates, Doctor of Philosophy, Philosophy
Skills:
Sram
Semiconductors
Drc
Lvs
Testing
Eda
Ic
Cmos
Asic
Vlsi
Simulations
Semiconductor Industry
Characterization
Design of Experiments
Static Timing Analysis
Thin Films
Semiconductor Process
Standard Cell
Physical Design
R&D
Research and Development
Languages:
English
Japanese
Mandarin

Publications

Us Patents

Methods For Crystallizing Metallic Oxide Dielectric Films At Low Temperature

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US Patent:
6432725, Aug 13, 2002
Filed:
Sep 28, 2001
Appl. No.:
09/966496
Inventors:
Jingyu Lian - Wallkill NY
Kwong Hon Wong - Wappingers Falls NY
Katherine Saenger - Ossining NY
Chenting Lin - Poughkeepsie NY
Assignee:
Infineon Technologies AG - Munich NY
International Business Machines Corporation - Armonk
International Classification:
H01L 2100
US Classification:
438 3, 438104, 438240
Abstract:
A method for forming a crystalline dielectric layer deposits an amorphous metallic oxide dielectric layer on a surface. The amorphous metallic oxide dielectric layer is treated with a plasma at a temperature of less than or equal to 400 degrees Celsius to form a crystalline layer.

Multi-Layer Pt Electrode For Dram And Fram With High K Dielectric Materials

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US Patent:
6794705, Sep 21, 2004
Filed:
Dec 28, 2000
Appl. No.:
09/751551
Inventors:
Jingyu Lian - Wallkill NY
Chenting Lin - Poughkeepsie NY
Nicolas Nagel - Yokohama, JP
Michael Wise - Lagrangeville NY
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L 27108
US Classification:
257310, 257295, 257296, 257303, 257304, 257311, 257906, 257908
Abstract:
A multi-layer electrode ( ) and method of fabrication thereof in which a conductive region ( ) is separated from a barrier layer ( ) by a first conductive liner ( ) and a second conductive liner ( ). First conductive layer ( ) comprises Pt, and second conductive liner ( ) comprises a thin layer of conductive oxide. The multi-layer electrode ( ) prevents oxygen diffusion through the top conductive region ( ) and reduces material variation during electrode patterning.

Device And Method For Inhibiting Oxidation Of Contact Plugs In Ferroelectric Capacitor Devices

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US Patent:
6984555, Jan 10, 2006
Filed:
Nov 3, 2003
Appl. No.:
10/702074
Inventors:
Jingyu Lian - Wallkill NY, US
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L 21/8242
US Classification:
438240, 438396, 438672
Abstract:
A ferroelectric capacitor device and method for producing such a device comprises forming a substrate, and forming a contact plug passing through the substrate. An electrically insulating layer is formed on the substrate, and a first electrode is formed on the electrically insulating layer. A ferroelectric layer is formed on the first electrode and a second electrode is formed on the ferroelectric layer. The first electrode is then electrically connected to the plug through the electrically insulating layer.

Self-Aligned V0-Contact For Cell Size Reduction

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US Patent:
7061035, Jun 13, 2006
Filed:
Oct 1, 2003
Appl. No.:
10/677852
Inventors:
Jingyu Lian - Wallkill NY, US
Nicolas Nagel - Kanagawa-ken, JP
Stefan Gernhardt - Kanagawa-ken, JP
Rainer Bruchhaus - Kanagawa-ken, JP
Andreas Hilliger - Kanagawa-ken, JP
Uwe Wellhausen - Dresden, DE
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L 29/94
US Classification:
257295, 257296, 257310
Abstract:
An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.

Adhesion Layer For Pt On Sio

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US Patent:
7270884, Sep 18, 2007
Filed:
Apr 7, 2003
Appl. No.:
10/408339
Inventors:
Jingyu Lian - Wallkill NY, US
Kwong Hon Wong - Wappingers Falls NY, US
Michael Wise - Larangeville NY, US
Young Limb - Poughkeepsie NY, US
Nicolas Nagel - Yokohama, JP
Assignee:
Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY
International Classification:
B32B 9/06
US Classification:
428446, 428450, 428469, 428630, 428670
Abstract:
Si, Al, Al plus TiN, and IrO2 are used as adhesion layers to prevent peeling of noble metal electrodes, such as Pt, from a silicon dioxide (SiO) substrate in capacitor structures of memory devices.

Multi-Layer Electrode And Method Of Forming The Same

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US Patent:
7319270, Jan 15, 2008
Filed:
Aug 30, 2004
Appl. No.:
10/929157
Inventors:
Jingyu Lian - Wallkill NY, US
Chenting Lin - Poughkeepsie NY, US
Nicolas Nagel - Yokohama, JP
Michael Wise - Lagrangeville NY, US
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L 23/48
H01L 23/52
H01L 29/40
H01L 27/10
H01L 29/74
US Classification:
257758, 257207, 257208, 257211, 257700, 257750, 257751, 257759, 257760, 257761, 257769, 257774
Abstract:
An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, formed from the same material as the first conductive layer, is deposited over the conductive liner.

Self-Aligned V0-Contact For Cell Size Reduction

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US Patent:
7378700, May 27, 2008
Filed:
Mar 9, 2006
Appl. No.:
11/373080
Inventors:
Jingyu Lian - Wallkill NY, US
Nicolas Nagel - Kanagawa-ken, JP
Stefan Gernhardt - Kanagawa-ken, JP
Rainer Bruchhaus - Kanagawa-ken, JP
Andreas Hilliger - Kanagawa-ken, JP
Uwe Wellhausen - Dresden, DE
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L 29/76
US Classification:
257295, 257296
Abstract:
An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.

Piezoelectric Stress Liner For Bulk And Soi

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US Patent:
7586158, Sep 8, 2009
Filed:
Jul 7, 2005
Appl. No.:
11/176727
Inventors:
Matthias Hierlemann - Fishkill NY, US
Jingyu Lian - Hopewell Junction NY, US
Rudolf Stierstorfer - Beacon NY, US
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L 29/76
US Classification:
257369, 257510, 257E27006
Abstract:
A preferred embodiment of the invention provides a semiconductor device. A preferred device comprises an n-channel transistor and a p-channel transistor disposed in a semiconductor body and a piezoelectric layer overlying the n-channel transistor and the p-channel transistor. In a preferred embodiment of the invention, the piezoelectric layer is biased to a first potential at a portion near the n-channel transistor and is biased to a second potential as a portion near the p-channel transistor.
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Jingyu Jenny Lian from Hopewell Junction, NY, age ~66 Get Report