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Jin Z Wallner

from Albany, NY
Age ~49
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Also known as:
Jin Zheng
Related to:
Kathy M Thomas, 64Frank J Thomas, 98Kate A Wallner, 35Anthony M Wallner, 71Jean M Wallner, 71Rachel J Wallner, 41Edward F Thomas, 36Ying Zheng, 52Thomas A Wallner, 44George W Wallner
Connected to:
Adrienne S Wallner, 42Anita L Wallner, 66Ann N Wallner, 67April D Wallner, 66Candace J Wallner, 78Connie B Wallner, 78Corinne D Wallner, 61Cortney L Wallner, 35Daniel E Wallner, 75Drew J Wallner, 30

Jin Wallner Phones & Addresses

  • Albany, NY
  • Pleasant Valley, NY
  • Poughkeepsie, NY
  • Fishkill, NY
  • Houghton, MI
  • Los Angeles, CA
  • Ashland, WI
  • 34 Beverly Dr, Albany, NY 12203

Work

Company: Globalfoundries Jul 2016 Position: Design enablement engineer

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Michigan Technological University 2001 to 2006

Skills

Matlab • Semiconductors • Simulations • C • C++ • Testing • Design of Experiments • Algorithms • Software Engineering • R&D • Nanotechnology • Characterization • Integrated Circuits • Software Development • Thin Films • Ic • Embedded Systems • Cmos

Languages

Mandarin

Ranks

Certificate: Machine Learning

Industries

Electrical/Electronic Manufacturing

Resumes

Resumes

Jin Wallner Photo 1

Design Enablement Engineer

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Location:
34 Beverly Dr, Albany, NY 12203
Industry:
Electrical/Electronic Manufacturing
Work:
Globalfoundries
Design Enablement Engineer
Ibm Sep 2010 - Jul 2016
Compact Model Engineer
Ibm Jan 2007 - Sep 2010
Process Engineer
Education:
Michigan Technological University 2001 - 2006
Doctorates, Doctor of Philosophy Zhejiang University 1997 - 2000
Master of Science, Masters, Communication Zhejiang University 1993 - 1997
Bachelors, Bachelor of Science, Biomedical Engineering
Skills:
Matlab
Semiconductors
Simulations
C
C++
Testing
Design of Experiments
Algorithms
Software Engineering
R&D
Nanotechnology
Characterization
Integrated Circuits
Software Development
Thin Films
Ic
Embedded Systems
Cmos
Languages:
Mandarin
Certifications:
Machine Learning

Publications

Us Patents

Multiple Exposure And Single Etch Integration Method

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US Patent:
8124534, Feb 28, 2012
Filed:
Jul 22, 2008
Appl. No.:
12/177690
Inventors:
Jin Wallner - Pleasant Valley NY, US
Thomas A. Wallner - Pleasant Valley NY, US
Ying Zhang - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/302
US Classification:
438705, 438712, 438719, 438723
Abstract:
A process including forming a silicon layer over a semiconductor wafer having features thereon and then selectively ion implanting in the silicon layer to form ion implanted regions. The step of selectively ion implanting is repeated as many times as necessary to obtain a predetermined number and density of features. Thereafter, the silicon layer is etched to form openings in the silicon layer that were formerly occupied by the ion implanted regions. The opened areas in the silicon layer form a mask for further processing of the semiconductor wafer.

Method For Transistor Fabrication With Optimized Performance

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US Patent:
20100078687, Apr 1, 2010
Filed:
Sep 30, 2008
Appl. No.:
12/242078
Inventors:
Da Zhang - Hopewell Junction NY, US
Christopher V. Baiocco - NewBurgh NY, US
Jie Chen - Singapore, SG
Weipeng Li - Beacon NY, US
Young Way Teh - Singapore, SG
Jin Wallner - Pleasant Valley NY, US
International Classification:
H01L 21/8238
H01L 29/04
US Classification:
257255, 438198, 257E21632, 257E29004
Abstract:
A semiconductor process and apparatus includes forming channel orientation CMOS transistors () with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer () over the PMOS and NMOS gate structures, etching the tensile etch stop layer () to form tensile sidewall spacers () on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer () over the NMOS and PMOS gate structures () and the tensile sidewall spacers (). In other embodiments, a first hydrogen-rich etch stop layer () is deposited and etched to form sidewall spacers () on the exposed gate sidewalls, and then a second tensile etch stop layer () is deposited over the NMOS and PMOS gate structures () and the sidewall spacers ().

Overlapping Contacts For Semiconductor Device

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US Patent:
20130001786, Jan 3, 2013
Filed:
Jun 29, 2011
Appl. No.:
13/171657
Inventors:
Brett H. Engel - Hopewell Junction NY, US
Lindsey Hall - Pleasant Valley NY, US
David F. Hilscher - Hopewell Junction NY, US
Randolph F. Knarr - Putnam Valley NY, US
Steven R. Soss - Cornwall NY, US
Jin Z. Wallner - Pleasant Valley NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
STMICROELECTRONICS, INC. - Coppell TX
GLOBALFOUNDRIES INC. - Grand Caymen
International Classification:
H01L 21/28
H01L 23/48
US Classification:
257761, 438656, 438652, 257E2301, 257E21158
Abstract:
A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.

Static Random Access Memory Test Structure

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US Patent:
20130094315, Apr 18, 2013
Filed:
Oct 14, 2011
Appl. No.:
13/273271
Inventors:
Oliver D. Patterson - Poughkeepsie NY, US
Jin Zheng Wallner - Pleasant Valley NY, US
Thomas A. Wallner - Pleasant Valley NY, US
Shenzhi Yang - Yorktown Heights NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G11C 29/00
US Classification:
365201
Abstract:
A static random access memory (SRAM) test structure includes a p-type source/drain implant region comprising contacts (CAs), wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of VCAs and rectangular contacts (CArecs), and wherein a CA or CArec in the ungrounded region is grounded during the inspection in the event of a short to a CA in the p-type source/drain implant region.

Overlapping Contacts For Semiconductor Device

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US Patent:
20130241070, Sep 19, 2013
Filed:
May 2, 2013
Appl. No.:
13/875443
Inventors:
Randolph F. Knarr - Putnam Valley NY, US
Steven R. Soss - Cornwall NY, US
Jin Z. Wallner - Pleasant Valley NY, US
Assignee:
International Business Machines Corporation - Armonk NY
STMicroelectronics, Inc. - Coppell TX
Globalfoundaries Inc. - Grand Caymen KY
International Classification:
H01L 23/528
US Classification:
257764
Abstract:
A semiconductor device with overlapping contacts is provided. In one aspect, the semiconductor device includes a dielectric layer; a first contact located in the dielectric layer; and a second contact located in the dielectric layer adjacent to the first contact, wherein a portion of the second contact overlaps a top surface of the first contact.

Multi-Layered Integrated Circuit With Selective Temperature Coefficient Of Resistance

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US Patent:
20160181239, Jun 23, 2016
Filed:
Dec 22, 2014
Appl. No.:
14/578678
Inventors:
- Armonk NY, US
Sungjae Lee - Schenectady NY, US
Edward J. Nowak - Essex Junction VT, US
Jin Z. Wallner - Albany NY, US
International Classification:
H01L 27/02
H01L 49/02
H01L 21/768
H01L 27/08
Abstract:
The integrated circuit described herein includes: a first resistor having a first trench in a dielectric layer, the first trench having a first width; a second resistor having a second trench in the dielectric layer, the second trench having a second width not equal to the first width; a trench in a dielectric layer; a first conductive layer having a first TCR and coating at least a portion of the first trench and the second trench; and a second conductive layer having a second TCR and coating at least a portion of the first conductive layer in each of the first trench and the second trench, wherein the second TCR is not equal to the first TCR, and wherein the TCR of the IC is selected based on a dimension of the trench, a thickness of the first conductive layer, and a thickness of the second conductive layer.

Method For Embedded Diamond-Shaped Stress Element

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US Patent:
20150340465, Nov 26, 2015
Filed:
May 23, 2014
Appl. No.:
14/285967
Inventors:
- Armonk NY, US
Judson R. Holt - Wappingers Falls NY, US
Jin Z. Wallner - Albany NY, US
Thomas A. Wallner - Albany NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/66
H01L 21/308
H01L 29/78
Abstract:
A method of manufacturing a semiconductor device with an embedded layer, by anisotropically etching a substrate adjacent to an already formed gate structure. A dummy layer is deposited in the previously etched region, and a second spacer is formed next to the first spacer. The dummy layer is removed, and a second anisotropic etch is performed. A semiconductor substrate is then epitaxially grown in the etched out region to form the embedded layer.

Finfet Formation With Late Fin Reveal

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US Patent:
20150255569, Sep 10, 2015
Filed:
Mar 7, 2014
Appl. No.:
14/200104
Inventors:
- Armonk NY, US
Myung-Hee Na - Lagrangeville NY, US
Jin Z. Wallner - Pleasant Valley NY, US
Thomas A. Wallner - Albany NY, US
Qintao Zhang - Mount Kisco NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H01L 29/66
Abstract:
A FinFET semiconductor device fabrication process includes forming a plurality of FinFET fins upon a semiconductor substrate, forming a first dielectric layer upon the semiconductor substrate so that an upper surface of the first dielectric layer is coplanar with upper surfaces of the FinFET fins, forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins, revealing the FinFET fins by removing first portions of the first dielectric layer from source-drain regions, removing the dummy gates, and subsequent to the removal of the dummy gates, revealing the FinFET fins by removing second portions of the first dielectric layer from channel regions.
Control profile
Jin Z Wallner from Albany, NY, age ~49 Get Report