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Jihong Choi

from San Diego, CA
Age ~58
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Also known as:
Ji Hong Choi
Related to:
Junghee ChoiHyun M Choi, 46
Connected to:
Alina Y Choi, 32Andy Choi, 35Angel J Choi, 46Antoinette T Choi, 77Antonio K Choi, 29Ariel R Choi, 31Asahi Choi, 45Barnabas M Choi, 67Bernadette Y Choi, 62Bitna Choi, 36

Jihong Choi Phones & Addresses

  • San Diego, CA
  • Milpitas, CA
  • 39939 Stevenson Blvd, Fremont, CA 94538 (510) 770-9324
  • Fishkill, NY
  • Berkeley, CA
  • Wappinger, NY
  • 8875 Costa Verde Blvd APT 1414, San Diego, CA 92122

Work

Company: Qualcomm Jan 2012 Address: Greater San Diego Area Position: Staff engineer

Education

Degree: Ph.D. School / High School: University of California, Berkeley 2003 to 2006 Specialities: Mechanical Engineering

Skills

Semiconductors • Design of Experiments • Design For Manufacturing • Cmos • Ic • Failure Analysis • Drc • Silicon • Simulations • Thin Films • Eda • Process Integration • Tcl • Manufacturing • Mems • Testing • Jmp • Semiconductor Manufacturing • Device Physics • Physical Verification • Dfm • Layout Tools • C++ • Matlab • Finite Element Analysis • Doe • Semiconductor Design Rules

Languages

English • Korean

Industries

Semiconductors

Resumes

Resumes

Jihong Choi Photo 1

Senior Staff Engineer

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Location:
10635 Carillon Ct, San Diego, CA 92131
Industry:
Semiconductors
Work:
Qualcomm - Greater San Diego Area since Jan 2012
Staff engineer
GLOBALFOUNDRIES Jun 2010 - Dec 2011
DFM&OPC engineer
GLOBALFOUNDRIES Mar 2009 - Jun 2010
Senior process development engineer
AMD Jan 2007 - Mar 2009
Senior process development engineer
Education:
University of California, Berkeley 2003 - 2006
Ph.D., Mechanical Engineering University of California, Berkeley 2001 - 2003
M.S., Mechanical Engineering Yonsei University 1994 - 2000
BS, Mechanical Engineering
Skills:
Semiconductors
Design of Experiments
Design For Manufacturing
Cmos
Ic
Failure Analysis
Drc
Silicon
Simulations
Thin Films
Eda
Process Integration
Tcl
Manufacturing
Mems
Testing
Jmp
Semiconductor Manufacturing
Device Physics
Physical Verification
Dfm
Layout Tools
C++
Matlab
Finite Element Analysis
Doe
Semiconductor Design Rules
Languages:
English
Korean

Publications

Us Patents

Methods Relating To Capacitive Monitoring Of Layer Characteristics During Back End-Of The-Line Processing

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US Patent:
8241927, Aug 14, 2012
Filed:
Oct 14, 2009
Appl. No.:
12/579216
Inventors:
Jihong Choi - Fishkill NY, US
Yongsik Moon - Paramus NJ, US
Roderick Augur - Hopewell Junction NY, US
Eden Zielinski - Wappingers Falls NY, US
Assignee:
Global Foundries, Inc. - Grand Cayman
International Classification:
H01L 21/66
US Classification:
438 17, 257529, 257773, 257E21531, 257774, 438667
Abstract:
Methods are provided that relate to the capacitive monitoring of characteristic pertaining to layer formed during the back end-of-the-line (BEOL) processing of a semiconductor device. In one embodiment, a method includes the steps of forming a first capacitor array including first and second overlying contacts each formed in a different one of the plurality of BEOL layers, measuring the interlayer capacitance between the first and second overlying contacts, and converting the measured interlayer capacitance to a distance between the first and second overlying contacts.

Cmp-First Damascene Process Scheme

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US Patent:
20110254139, Oct 20, 2011
Filed:
Apr 20, 2010
Appl. No.:
12/763550
Inventors:
Jihong Choi - Fishkill NY, US
Tibor Bolom - Wappingers Falls NY, US
Assignee:
GLOBALFOUNDRIES Inc. - Grand Cayman
International Classification:
H01L 23/535
H01L 23/58
H01L 21/441
US Classification:
257632, 438618, 257E2146, 257E21477, 257E23168
Abstract:
An improved metal interconnect is formed with reduced metal voids and dendrites. An embodiment includes forming a mask layer on a dielectric layer, forming openings in the mask and dielectric layers, depositing a planarization layer over the mask layer and filling the openings, planarizing to remove the mask layer, removing the planarization layer from the openings, and filling the openings with metal. The planarization step prior to depositing the metal removes the etch undercut that occurs during formation of the openings and reduces the aspect ratio in the openings, thereby improving metal fill uniformity.

Metal Finger Capacitors With Hybrid Metal Finger Orientations In Stack With Unidirectional Metal Layers

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US Patent:
20130320494, Dec 5, 2013
Filed:
Dec 20, 2012
Appl. No.:
13/721089
Inventors:
PR Chidambaram - San Diego CA, US
Lixin Ge - San Diego CA, US
Bin Yang - San Diego CA, US
Jihong Choi - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H01L 49/02
US Classification:
257532, 438396
Abstract:
A semiconductor die having a plurality of metal layers, including a set of metal layers having a preferred direction for minimum feature size. The set of metal layers are such that adjacent metal layers have preferred directions orthogonal to one another. Finger capacitors formed in the set of metal layers are such that a finger capacitor formed in one metal layer has a finger direction parallel to the preferred direction of that metal layer. In bidirectional metal layers, capacitor fingers may be in either direction.

Contact For Semiconductor Device

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US Patent:
20180076139, Mar 15, 2018
Filed:
Nov 15, 2016
Appl. No.:
15/352342
Inventors:
- San Diego CA, US
Haining YANG - San Diego CA, US
Youseok SUH - San Diego CA, US
Jihong CHOI - San Diego CA, US
Junjing BAO - San Diego CA, US
International Classification:
H01L 23/535
H01L 23/532
H01L 21/768
Abstract:
A semiconductor device may include a source/drain contact trench adjacent to a gate. The source/drain contact trench may include a first portion and a second portion on the first portion. The semiconductor device also may include an insulating contact spacer liner within the source/drain contact trench. The insulating contact spacer liner contacts the first portion but not the second portion of the source/drain contact trench. The semiconductor device may further include a conductive material within the insulating contact spacer liner and the second portion of the source/drain contact trench. The conductive material may land in a source/drain region of the semiconductor device.

Systems And Methods To Reduce Parasitic Capacitance

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US Patent:
20160293475, Oct 6, 2016
Filed:
Apr 1, 2015
Appl. No.:
14/676728
Inventors:
- San Diego CA, US
Vidhya Ramachandran - Cupertino CA, US
Christine Sung-An Hau-Riege - Fremont CA, US
John Jianhong Zhu - San Diego CA, US
Jeffrey Junhao Xu - San Diego CA, US
Jihong Choi - San Diego CA, US
Jun Chen - San Diego CA, US
Choh Fei Yeap - San Diego CA, US
International Classification:
H01L 21/768
H01L 23/532
Abstract:
Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.

Semiconductor Device Having High Mobility Channel

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US Patent:
20150091060, Apr 2, 2015
Filed:
Sep 27, 2013
Appl. No.:
14/040366
Inventors:
- San Diego CA, US
PR Chidambaram - San Diego CA, US
John Jianhong Zhu - San Diego CA, US
Jihong Choi - San Diego CA, US
Da Yang - San Diego CA, US
Ravi Mahendra Todi - San Diego CA, US
Giridhar Nallapati - San Diego CA, US
Chock Hing Gan - San Diego CA, US
Ming Cai - San Diego CA, US
Samit Sengupta - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H01L 29/66
H01L 29/778
US Classification:
257194, 438172
Abstract:
In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel

Complementary Back End Of Line (Beol) Capacitor

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US Patent:
20150028452, Jan 29, 2015
Filed:
Oct 10, 2014
Appl. No.:
14/512191
Inventors:
- San Diego CA, US
Bin YANG - San Diego CA, US
PR CHIDAMBARAM - San Diego CA, US
Lixin GE - San Diego CA, US
Jihong CHOI - San Diego CA, US
International Classification:
H01L 23/522
H01L 49/02
US Classification:
257532
Abstract:
A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes a lower interconnect layer of the interconnect stack. The CBC structure also includes a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes a metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure also includes a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having a portion of the first upper interconnect layer, and a second capacitor plate having a portion of the MIM capacitor layer(s).

Complementary Back End Of Line (Beol) Capacitor

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US Patent:
20140231957, Aug 21, 2014
Filed:
Feb 19, 2013
Appl. No.:
13/770127
Inventors:
- San Diego CA, US
Bin Yang - San Diego, US
PR Chidambaram - San Diego CA, US
Lixin Ge - San Diego CA, US
Jihong Choi - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H01L 23/538
H01L 27/08
US Classification:
257532, 438381
Abstract:
A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s).
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Jihong Choi from San Diego, CA, age ~58 Get Report