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Jiangqi Q He

from Mesa, AZ
Age ~54
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Also known as:
Jun He, He Jiangqi
Phone and address:
3508 E Jaeger Cir, Mesa, AZ 85213
Related to:
Gordon HeShanshan Shan Zeng, 49
Connected to:
Baokun He, 49Bo He, 48Bryan D He, 30Camille A He, 45Chenxu He, 46Congzhou He, 52Dajiang He, 71Denis He, 34Diana He, 30Dingshan He, 46

Jiangqi He Phones & Addresses

  • 3508 E Jaeger Cir, Mesa, AZ 85213
  • Las Cruces, NM
  • 375 Federal St, Chandler, AZ 85226 (480) 857-6529
  • 1179 Mesquite St, Gilbert, AZ 85233 (480) 857-6529
  • Durham, NC
  • Maricopa, AZ

Work

Position: Chief architect and head of hardware engineering lab

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Duke University 1997 to 2000 Specialities: Computer Engineering, Philosophy

Skills

Semiconductors

Interests

Power Delivery For Data Center • Validation and Testing Methdologies • Voltage Regulator • Signal Integrity • Power Integrity • Computational Electromagnetics • Packaging Technologies • Server Platform Designs

Industries

Semiconductors

Resumes

Resumes

Jiangqi He Photo 1

Chief Architect And Head Of Hardware Engineering Lab

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Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Semiconductors
Work:

Chief Architect and Head of Hardware Engineering Lab
Intel Corporation
Principal Engineer at Intel Corporation
Education:
Duke University 1997 - 2000
Doctorates, Doctor of Philosophy, Computer Engineering, Philosophy Xiamen University 1988 - 1992
Bachelors, Bachelor of Science, Physics
Skills:
Semiconductors
Interests:
Power Delivery For Data Center
Validation and Testing Methdologies
Voltage Regulator
Signal Integrity
Power Integrity
Computational Electromagnetics
Packaging Technologies
Server Platform Designs

Business Records

Name / Title
Company / Classification
Phones & Addresses
Jiangqi He
PHOENIX INTERNATIONAL GROUP LLC
1022 W Horseshoe Ave, Gilbert, AZ 85233
3508 E Jaeger Cir, Mesa, AZ 85213
Jiangqi He
Principal
Jiangqi Investment LLC
Investor
3508 E Jaeger Cir, Mesa, AZ 85213

Publications

Us Patents

Power/Ground Configuration For Low Impedance Integrated Circuit

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US Patent:
6784532, Aug 31, 2004
Filed:
Jul 31, 2002
Appl. No.:
10/209847
Inventors:
Dong Zhong - Chandler AZ
Farzaneh Yahyaei-Moayyed - Chandler AZ
David G. Figueroa - Mesa AZ
Chris Baldwin - Chandler AZ
Jiangqi He - Chandler AZ
Yuan-Liang Li - Chandler AZ
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2352
US Classification:
257691, 257668, 257692
Abstract:
An integrated circuit including a die, a power terminal and a ground terminal all mounted onto a substrate. The power terminal including a body and a first extension projecting from the body, and the ground terminal including a body and a second extension projecting from the body. The second extension on the ground terminal being adjacent to the first extension on the power terminal to offset inductance that is generated by supplying current to the die through the power terminal.

Electronic Assembly

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US Patent:
6803649, Oct 12, 2004
Filed:
May 16, 2003
Appl. No.:
10/440322
Inventors:
Jiangqi He - Chandler AZ
Jung Kang - Chandler AZ
Dong Zhong - Chandler AZ
Yuan-Liang Li - Chandler AZ
John Tang - Phoenix AZ
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2352
US Classification:
257691, 257774, 257723, 257775
Abstract:
According to one aspect of the invention, a electronic assembly is provided. The electronic assembly includes a motherboard, a first microelectronic die on a package substrate, a second microelectronic die, and a strip of flex tape interconnecting the microelectronic dies. The package substrate has a metal core with via openings, power conductors connecting a top and bottom surface of the substrate and passing through the via openings, and ground conductors interconnecting the metal core with the top and bottom surface of the package substrate. The flex tape has signal conductors which interconnect the microelectronic dies. Power is provided to the first microelectronic die via the power conductors. IO signals are sent between the microelectronic dies over the signal conductors in the flex tape.

Silicon Building Blocks In Integrated Circuit Packaging

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US Patent:
6815256, Nov 9, 2004
Filed:
Dec 23, 2002
Appl. No.:
10/329190
Inventors:
David Gregory Figueroa - Mesa AZ
Dong Zhong - San Jose CA
Yuan-Liang Li - Chandler AZ
Jiangqi He - Gilbert AZ
Cengiz Ahmet Palanduz - Chandler AZ
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2144
US Classification:
438113, 357 236, 357 234, 357 2311, 136201, 438745, 438753
Abstract:
An improved silicon building block is disclosed. In an embodiment, the silicon building block has at least two vias through it. The silicon building block is doped and the vias filled with a first material, and, optionally, selected ones of the vias filled instead with a second material. In an alternative embodiment, regions of the silicon building block have metal deposited on them.

Vertical Capacitor Apparatus, Systems, And Methods

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US Patent:
6885544, Apr 26, 2005
Filed:
Sep 24, 2003
Appl. No.:
10/669678
Inventors:
Hyunjun Kim - Chandler AZ, US
Jiangqi He - Gilbert AZ, US
Dong-Ho Han - Pheonix AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01G004/06
US Classification:
3613211, 3613215, 3613012, 3613061, 3613063, 361311, 361313
Abstract:
An apparatus and system, as well as fabrication methods therefor, may include a plurality of vertically-oriented plates separated by dielectric layers, wherein the vertically-oriented plates include a plurality of terminals coupled to a bottom side of the plates.

Circuit Board With Trace Configuration For High-Speed Digital Differential Signaling

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US Patent:
6914334, Jul 5, 2005
Filed:
Jun 12, 2002
Appl. No.:
10/167904
Inventors:
Yuan-Liang Li - Chandler AZ, US
Jiangqi He - Chandler AZ, US
Dong Zhong - Chandler AZ, US
David G. Figueroa - Mesa AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L023/48
US Classification:
257752, 257758, 361792, 174255
Abstract:
Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

Low Impedance, High-Power Socket And Method Of Using

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US Patent:
6964584, Nov 15, 2005
Filed:
Dec 21, 2001
Appl. No.:
10/032377
Inventors:
Dong Zhong - Chandler AZ, US
Yuan-Liang Li - Chandler AZ, US
David G. Figueroa - Mesa AZ, US
Jiangqi He - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01R013/66
US Classification:
439620
Abstract:
The present invention relates to a power socket for a microelectronic device that, in one embodiment, uses a low-resistance power and ground terminal configuration. In another embodiment, a low-resistance power and ground terminal configuration is combined on the power socket with a vertically oriented interdigital capacitor that is used to lower inductance. By this combination a significantly lowered impedance is achieved during operation of the microelectronic device. The capacitor may include plates that are vertically oriented relative to the major planar surface of the socket faces and capacitors may be located between a power and a ground contact, between two power contacts, or between two ground contacts.

Silicon Building Block Architecture With Flex Tape

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US Patent:
6995465, Feb 7, 2006
Filed:
Jun 4, 2003
Appl. No.:
10/455908
Inventors:
Dong Zhong - Chandler AZ, US
Yuan-Liang Li - Chandler AZ, US
Jiangqi He - Chandler AZ, US
Jung Kang - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/48
US Classification:
257692, 257700
Abstract:
An apparatus is constituted with an integrated circuit and a flex tape coupled to the integrated circuit. The flex tape is employed to facilitate ingress/egress of signals to/from the integrated circuit. In one embodiment, the flex tape includes a plurality of signal traces. In another embodiment, the apparatus also includes a silicon interposer coupled to the flex tape and a substrate coupled to the silicon interposer.

Extended Thin Film Capacitor (Tfc)

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US Patent:
7027289, Apr 11, 2006
Filed:
Mar 25, 2004
Appl. No.:
10/808489
Inventors:
Jiangqi He - Gilbert AZ, US
Ping Sun - Gilbert AZ, US
Hyunjun Kim - Chandler AZ, US
Xiang Yin Zeng - Shanghai, CN
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01G 4/228
US Classification:
3613062, 3613014, 361303, 3613212, 361311, 361313, 438250, 438253, 438587, 438588, 257532, 257534
Abstract:
Extending high k material of a second dielectric layer to surround at least one thru-via designed to provide a signal other than a power signal to a die may eliminate discrete AC coupling capacitors to reduce cost and improve performance of the package.
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Jiangqi Q He from Mesa, AZ, age ~54 Get Report