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Jesse T Quatse

from Mill Valley, CA
Age ~89
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Also known as:
Jesse Dr Quatse, Jesse P Quatse, Jessica Veronica Quatse, Jessie T Quatse, Veronica Quatse, Cheryl Quatse, Joseph Klug, Jesie E
Phone and address:
203 Morning Sun Ave, Mill Valley, CA 94941
(415) 383-8332
Related to:
Franika HartAndrea B Quatse, 62Celeste H Longway, 64Jessica V Quatse, 44Veronica L Quatse, 43Cheryl A Quatse
Connected to:
Alder M Quattlebaum, 39Andrew H Quattlebaum, 90Dru L Quattlebaum, 39Isaac Quattlebaum, 76James M Quattlebaum, 72Jasmine Quattlebaum, 34Jeanne R Quattlebaum, 60Jeffery Quattlebaum, 40Katelyn Quattlebaum, 32Lee C Quattlebaum, 30

Jesse Quatse Phones & Addresses

  • 203 Morning Sun Ave, Mill Valley, CA 94941 (415) 383-8332 (415) 388-2865
  • 31 Reed Blvd APT 14A, Mill Valley, CA 94941
  • 46 Eucalyptus Knoll St, Mill Valley, CA 94941 (415) 383-8332 (415) 388-2865
  • 13 Eucalyptus Knoll St, Mill Valley, CA 94941
  • Berkeley, CA
  • Los Angeles, CA
  • Tiburon, CA
  • Larkspur, CA
  • Corte Madera, CA
  • Capac, MI

Resumes

Resumes

Jesse Quatse Photo 1

Jesse Quatse

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Location:
San Francisco Bay Area
Industry:
Computer Software
Skills:
JavaScript
XML
MySQL
Java
AJAX
Microsoft Office
HTML
PHP
CSS
Scrum
MS Project
SQL Server
C
Apache
Windows
XHTML
Visual Basic
UML
J2EE
DHTML
Web Services
Start-ups
jEdit
Agile
SQL
Software Development
Agile Methodologies
Microsoft SQL Server
Java Enterprise Edition
Languages:
French
Jesse Quatse Photo 2

Jesse Quatse

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Jesse Quatse
Vice-President
Designmind Inc
Custom Computer Programing
1900 Powell St, Oakland, CA 94608
Jesse Quatse
Vice-President
DESIGNMIND BUSINESS SOLUTIONS
Custom Computer Software Services · Custom Computer Programing · Computer Sales
150 Spear St SUITE 700, San Francisco, CA 94105
465 California St, San Francisco, CA 94104
1900 Powell St, Oakland, CA 94608
939 61 St, Emeryville, CA 94608
(415) 538-8484, (415) 276-3252
Jesse T. Quatse
President
DIGITAL AUTOMATION CORPORATION
21 Tamal Vis #200, Corte Madera, CA 94925
Jesse T. Quatse
President
MICROFAST CORPORATION
18 Corte Del Bayo, Larkspur, CA 94939
Jesse T. Quatse
President
HYPERGRAF INC
Business Services at Non-Commercial Site
203A Morningsun Ave, Mill Valley, CA 94941
203 Morning Sun Ave, Mill Valley, CA 94941

Publications

Wikipedia

Jess Quatse

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Jesse Quatse (April 4, 1908 December 26, 1977) was an American football offensive tackle in the National Football League for the Green Bay Packers, ...

Us Patents

High-Precision Customer-Based Targeting By Individual Usage Statistics

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US Patent:
8412566, Apr 2, 2013
Filed:
Jul 8, 2003
Appl. No.:
10/616486
Inventors:
Jesse T. Quatse - Mill Valley CA, US
Anssi Karhinen - Helsinki, FI
Eric G. Wasserman - Berkeley CA, US
Assignee:
YT Acquisition Corporation - Delray Beach FL
International Classification:
G06Q 30/00
US Classification:
705 141
Abstract:
A system for distributing limited numbers of promotional offers to individual customers, the promotional offers being targeted to customers based on the customers' individual probabilities of accepting the offers in such a way that each customer can receive a limited number of offers that are estimated to be most likely to be acceptable by the customer. Customer-Based targeting analyzes each customer's past purchasing behavior relative to a master list of promotional offers made available to all customers. From that master list Customer-Based targeting selects a preset limit of promotional offers for each individual customer according to the likelihood that, given the opportunity to select any offers of the master list, each customer would prefer those few offers selected specifically for the customer. Various techniques are disclosed for providing an offer acceptance probability profile tailored for individual customers for use in the Customer-Based targeting technique. Product groupings and market segments are taken into account.

High-Precision Customer-Based Targeting By Individual Usage Statistics

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US Patent:
20090177540, Jul 9, 2009
Filed:
Jun 6, 2008
Appl. No.:
12/134904
Inventors:
Jesse T. Quatse - Mill Valley CA, US
Assignee:
YT ACQUISITION CORPORATION - Rye Brook NY
International Classification:
G06Q 30/00
G06Q 90/00
US Classification:
705 14
Abstract:
A system for distributing limited numbers of promotional offers targeted to individual customers based on the customers' individual probabilities of accepting the offers is disclosed. Each customer can receive a limited number of offers estimated to be most likely to be acceptable by the customer. Customer-Based targeting analyzes each customer's past purchasing behavior relative to a master list of promotional offers made available to all customers and selects a number of promotional offers most likely to be preferred by each customer. Various techniques, such as empirical Bayes techniques and sparse data handling techniques, are disclosed for providing an offer acceptance probability profile tailored for individual customers. Product groupings and market segments are taken into account. Various marketing strategies are incorporated into the system. An individual can override a system computation and manually set the relative offer acceptance probabilities for an individual user or class of users using a graphical technique.

Electronic Postage Meter Having Improved Security And Fault Tolerance Features

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US Patent:
44843070, Nov 20, 1984
Filed:
Feb 16, 1982
Appl. No.:
6/349285
Inventors:
Jesse T. Quatse - Sausalito CA
Donald E. Dodge - San Francisco CA
Richard K. Dove - Piedmont CA
Assignee:
f.m.e. Corporation - Hayward CA
International Classification:
G06F 1520
US Classification:
364900
Abstract:
A microcomputerized postage meter that provides high degrees of security and fault tolerance. The meter maintains data security under low power conditions by the use of functionally nonvolatile memory units. Register and other data which must survive normal and abnormal losses of power to the meter electronics are stored in dual redundant battery augmented memories (hereinafter designated BAMs). Upon detecting an error condition, the microcomputer writes an appropriate fault code to the BAMs. A mechanism for disabling the meter includes dual redundant flip-flops which are set to a "faulted" state upon detection by the microcomputer of a failure condition. These flip-flops are powered by the BAM batteries. They cannot be reset except by physical access to the meter interior, which access is only available to authorized personnel at the factory. The fault flip-flops are also set when the microcomputer fails to properly execute its own operating program.

Serial Information Transfer Protocol

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US Patent:
46835300, Jul 28, 1987
Filed:
Apr 10, 1984
Appl. No.:
6/598644
Inventors:
Jesse T. Quatse - Corte Madera CA
Assignee:
Telemecanique Electrique - Nanterre Cedex
International Classification:
G06F 1342
US Classification:
364200
Abstract:
An interconnecting transparent serial bus for extending a parallel CPU domain to a parallel peripheral module domain includes a bidirectional serial protocol for transferring information between the CPU and one or more peripheral module controllers, referred to as rack masters. Each rack master provides a parallel path to any number of peripheral modules associated therewith. Serial bus protocol includes a frame line, defining a synchronous information exchange interval; a clock line, for propagating a synchronous information clock signal during the information exchange interval; a sync line, for propagating a sync signal to identify one or more discrete asynchronous information fields during the information exchange interval; and a signal line for propagating data, address, and control information between the CPU and its associated rack masters in serial fashion.

Programmable Controller ("Pc") With Co-Processing Architecture

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US Patent:
48706140, Sep 26, 1989
Filed:
Dec 29, 1988
Appl. No.:
7/292623
Inventors:
Jesse T. Quatse - Tiburon CA
International Classification:
G06F 900
US Classification:
364900
Abstract:
A programmable controller architecture utilizes specialized processors in a co-processing system so that each function is optimized. The system comprises first and second processors having respective instruction sets and respective associated means for fetching instructions from a common memory. Each of the processors and its instruction set is tailored to a corresponding processor's specialized function. Each processor's instruction set includes a subset of special instructions, the occurrence of one of which signifies that control is to be passed from one processor to the other. Upon encountering a special instruction within its special instruction subset, a given processor invokes associated control passing circuitry for suspending its own operation and commencing the operation of the other processor. The passage of control occurs very quickly so that the speed benefits of switching control are not lost in the overhead of such switching. Since passage of control renders one of the processors inactive, there is no requirement that the actual instructions of one processor be objectively distinguishable from those of the other.

Boolean Processor For A Progammable Controller

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US Patent:
47165413, Dec 29, 1987
Filed:
Aug 2, 1984
Appl. No.:
6/637772
Inventors:
Jesse T. Quatse - Corte Madera CA
International Classification:
G06F 922
G06F 900
G05B 1918
US Classification:
364900
Abstract:
A very fast and efficient Boolean processor ("BP") (20) capable of compiling a full range of diagrams or expressions in ladder, logigram, and Boolean with a small but powerful instruction set. The BP includes an instruction decoder (34), combinatoric logic (35), a T-register (42) which holds the temporary results of a sequential AND operation, an N-register (43) which holds the initial Boolean value of T, a Binary Accumulator Memory ("BAM") (40) which is used as a scratchpad for a program which evaluates a ladder or logigram diagram or a Boolean expression, a source address ("S") in BAM (40) from which an initial operand is taken, a destination address ("D") in BAM (40) in which the result of an operation is stored, and a destination address register ("DAR") (45) in which the destination address is stored. The instruction set includes a subset of input instructions and a subset of structure instructions. The operand (I) of an input instruction is an address in IOIM (25).

Method And Apparatus For Protecting And Monitoring The Transmission Of Information Between The Central Unit Of A Programmable Controller And The Sensors And/Or The Actuators Of The Controlled Process

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US Patent:
47746564, Sep 27, 1988
Filed:
Feb 1, 1985
Appl. No.:
6/704250
Inventors:
Jesse T. Quatse - Corte Madera CA
Lionel Heitz - Crolles, FR
Jacky Pergent - Carros Le Neuf, FR
Olivier Penot - Antibes, FR
Assignee:
La Telemecanique Electrique
International Classification:
G06F 902
US Classification:
364900
Abstract:
An input/output device is used for a programmable controller having on input/output cards a plurality of electronic channels forming the logic interfaces between the connection bus with the central unit and the sensors or the actuators connected to the controllers; this device further uses electronic circuits for monitoring the good transmission of input/output signals by the adaptation interfaces providing for the galvanic isolation of the bus with respect to the sensors and actuators of the controlled automatism.

Error Control Apparatus Using Restore Memory For Recovering From Parity Discordances In Transmissions Between Controller And Real-Time I/O Devices

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US Patent:
48645311, Sep 5, 1989
Filed:
Sep 28, 1987
Appl. No.:
7/102255
Inventors:
Jesse T. Quatse - Corte Madera CA
Lionel Heitz - Crolles, FR
Jacky Pergent - Carros le Neuf, FR
Olivier Penot - Antibes, FR
Assignee:
La Telemecanique Electrique
International Classification:
G06F 1110
G06F 1546
US Classification:
364900
Abstract:
An input/output device monitors the transmission of information between a processor of a programmable controller and sensors and actuators of a process to be controlled. This device includes electronic circuits adapted for calculating the parities of the digital words which pass therethrough, these parities being compared with corresponding parities calculated by the processor which thereafter invalidates the words having two different parities.
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Jesse T Quatse from Mill Valley, CA, age ~89 Get Report