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Jerry G Fossum

from Gainesville, FL
Age ~81

Jerry Fossum Phones & Addresses

  • 4529 NW 53Rd St, Gainesville, FL 32606 (352) 377-5887
  • Palm Harbor, FL
  • North Pole, AK

Business Records

Name / Title
Company / Classification
Phones & Addresses
Jerry Fossum
Director
APPLIED NOVEL DEVICES, INC
15844 Garrison Cir, Austin, TX 78717
4529 NW 53 St, Gainesville, FL 32606
Jerry Fossum
Director Of Telecommunications
North Dakota Office of Management and Budget
Public Finance/Taxation/Monetary Policy · Central Services · Central Supply Service · State Procurement Office · Data Processing and Tele-Communications Service · Personnel Office · Human Services · Facility Management
(701) 328-2770, (701) 328-2780, (701) 328-3346, (701) 328-2683

Publications

Us Patents

Body-Tied-To-Body Soi Cmos Inverter Circuit

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US Patent:
6498371, Dec 24, 2002
Filed:
Jul 31, 2001
Appl. No.:
09/919543
Inventors:
Srinath Krishnan - Campbell CA
Jerry G. Fossum - Gainesville FL
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 310392
US Classification:
257351, 251347, 251348, 251349, 438154, 438199, 438967
Abstract:
An SOI CMOS inverter circuit in which a silicide layer in combination with body tie regions tie a p-type body region and an n-type body region together. At the same time, however, the body regions remain floating electrically so that the benefits of SOI are maintained. The silicide layer permits excess carriers to be recombined via the respective body regions so that the body region potential does not get modulated by generation/recombination effects. Thus, a hysteresis effect in the inverter circuit will be reduced.

Body-Tied-To-Body Soi Cmos Inverter Circuit

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US Patent:
6630376, Oct 7, 2003
Filed:
Oct 31, 2002
Appl. No.:
10/284839
Inventors:
Srinath Krishnan - Campbell CA
Jerry G. Fossum - Gainesville FL
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 218238
US Classification:
438199, 438479
Abstract:
An SOI CMOS inverter circuit in which a silicide layer in combination with body tie regions tie a p-type body region and an n-type body region together. At the same time, however, the body regions remain floating electrically so that the benefits of SOI are maintained. The silicide layer permits excess carriers to be recombined via the respective body regions so that the body region potential does not get modulated by generation/recombination effects. Thus, a hysteresis effect in the inverter circuit will be reduced.

Hybrid-Fet And Its Application As Sram

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US Patent:
7470951, Dec 30, 2008
Filed:
Jan 31, 2005
Appl. No.:
11/047543
Inventors:
Leo Mathew - Austin TX, US
Jerry G. Fossum - Gainesville FL, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 29/94
US Classification:
257327, 257328, 257329, 257350, 257347, 257348, 257349, 257E51005
Abstract:
A semiconductor device () is provided herein. The semiconductor device comprises (a) a substrate (), a semiconductor layer () disposed on said substrate and comprising a horizontal region () and a fin which extends above, and is disposed adjacent to, said horizontal region, and (c) at least one channel region () defined in said fin and in said horizontal region.

Two-Transistor Floating-Body Dynamic Memory Cell

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US Patent:
8498140, Jul 30, 2013
Filed:
Oct 1, 2008
Appl. No.:
12/681289
Inventors:
Jerry G. Fossum - Gainesville FL, US
Leo Mathew - Austin TX, US
Michael Sadd - Austin TX, US
Vishal P. Trivedi - Chandler AZ, US
Assignee:
University of Florida Research Foundation, Inc. - Gainesville FL
International Classification:
G11C 5/02
G11C 5/06
G11C 7/00
G11C 11/401
G11C 11/4063
G11C 11/40
US Classification:
365 72, 365 51, 365 63, 365184, 365189011, 257347, 257E27111
Abstract:
Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.

Floating-Body/Gate Dram Cell

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US Patent:
20110222337, Sep 15, 2011
Filed:
Dec 29, 2009
Appl. No.:
13/124066
Inventors:
Jerry G. Fossum - Gainesville FL, US
Zhichao Lu - Santa Clara CA, US
Assignee:
University of Florida Research Foundation, Inc. - Gainesville FL
International Classification:
G11C 11/36
H01L 27/12
US Classification:
365175, 257347, 257E27112
Abstract:
Memory cell structures and biasing schemes are provided. Certain embodiments pertain to a modified floating-body gate cell, which can provide improved retention times. In one embodiment, a gated diode is used to drive the gate of a second transistor structure of a cell. In another embodiment, a body-tied-source (BTS) field effect transistor is used to drive the gate of the second transistor structure of a cell.

Oxide Charge Induced High Low Junction Emitter Solar Cell

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US Patent:
43439624, Aug 10, 1982
Filed:
Feb 2, 1981
Appl. No.:
6/230682
Inventors:
Arnost Neugroschel - Gainesville FL
Shing-Chong Pao - Gainesville FL
Fred A. Lindholm - Gainesville FL
Jerry G. Fossum - Gainesville FL
International Classification:
H01L 3106
US Classification:
136255
Abstract:
A high-low junction emitter silicon solar cell including an electron accumulation layer formed by oxide-charge-induction.

Oxide Charge Induced High Low Junction Emitter Solar Cell

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US Patent:
44830637, Nov 20, 1984
Filed:
Jun 1, 1982
Appl. No.:
6/383617
Inventors:
Arnost Neugroschel - Gainesville FL
Shing-Chong Pao - Gainesville FL
Fred A. Lindholm - Gainesville FL
Jerry G. Fossum - Gainesville FL
Assignee:
University of Florida - Gainesville FL
International Classification:
H01L 3118
H01L 3106
US Classification:
29572
Abstract:
A method of forming a high-low junction emitter silicon solar cell including the producing of an electron accumulation layer by oxide-charge-induction.

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Jerry G. Fossum

Jerry G Fossum from Gainesville, FL, age ~81 Get Report