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Jerome L Cann

from Nellysford, VA
Age ~57
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Also known as:
Jerome Luther Cann, Jerald L Cann
Related to:
Jacob D Cann, 28
Connected to:
Alex Cann, 31Alexandra M Cann, 59Alfred J Cann, 98Arthur H Cann, 46Brett B Cann, 36Byron A Cann, 40Courtney Cann, 36Darren K Cann, 59Denise S Cann, 53Emmanuel A Cann, 58

Jerome Cann Phones & Addresses

  • Nellysford, VA
  • 555 Geese Lndg, Glen Allen, VA 23060 (802) 899-9988
  • McLean, VA
  • Huntington, VT
  • 4 Country View Dr, Jericho, VT 05465 (802) 899-9988
  • Helotes, TX
  • Jonesville, VT
  • Harpers Ferry, WV
  • Silver Spring, MD
  • Colorado Springs, CO

Work

Company: Ibm Jul 2010 Address: Essex Junction, Vermont Position: Senior systems administrator, intellectual property law

Education

Degree: BS School / High School: University of Maryland College Park 1994 to 1998 Specialities: Electrical Engineering

Skills

Testing • Semiconductors • Unix • Databases • Integration • Software Development • Debugging • Perl • Programming • Linux • Hardware • Shell Scripting • Enterprise Software • Patents • Requirements Analysis • Java • Software Engineering • Unix Shell Scripting • Analysis • Embedded Systems • Technical Leadership • Db2 • Simulations • Agile Methodologies • Business Process • Sql • Intellectual Property • C++ • Public Speaking • Systems Engineering • Test Automation • Cloud Computing • Computer Architecture • Data Mining • Xml • Information Technology • Visual Basic • Information Security • Electrical Engineering • Matlab • System Architecture • Defense • Technical Analysis • Microelectronics • Visual Studio • Eclipse • Java Enterprise Edition • Scaled Agile Framework • Product Management • Safe

Languages

English

Awards

The army commendation medal - Department... • The army commendation medal - Department... • The army achievement medal - Department ... • First place, district 45, division g, in... • First place, district 45, division g, in...

Ranks

Certificate: Top Secret Security Clearance (Ts/Ssbi)

Interests

Solving Problems Through Technology • Education • Playing the Piano • Science and Technology • Devouring Technological Information

Industries

Information Technology And Services

Resumes

Resumes

Jerome Cann Photo 1

Senior Software Engineer

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Location:
555 Geese Lndg, Glen Allen, VA 05877
Industry:
Information Technology And Services
Work:
IBM - Essex Junction, Vermont since Jul 2010
Senior Systems Administrator, Intellectual Property Law
IBM - Essex Junction, Vermont Aug 1998 - Jul 2010
Test Systems Engineer & Senior Business Counsel, Systems & Technology Group
Cadence Design Systems - Columbia, Maryland Jun 1996 - Jul 1998
Engineering Intern
Facilities Development Corporation - Washington D.C. Metro Area Jun 1995 - Aug 1995
Construction Surveillance Technician (TS/SBI)
Beta Analytics, Inc - La Paz, Bolivia and Tel Aviv, Israel Nov 1993 - Dec 1994
Construction Surveillance Technician (TS/SBI)
Education:
University of Maryland College Park 1994 - 1998
BS, Electrical Engineering US Diplomatic Security Training Center (DSTC) 1993 - 1993
Construction Surveillance Technician (CST), Technical Surveillance Countermeasures (TSCM) US Naval Academy 1985 - 1987
Skills:
Testing
Semiconductors
Unix
Databases
Integration
Software Development
Debugging
Perl
Programming
Linux
Hardware
Shell Scripting
Enterprise Software
Patents
Requirements Analysis
Java
Software Engineering
Unix Shell Scripting
Analysis
Embedded Systems
Technical Leadership
Db2
Simulations
Agile Methodologies
Business Process
Sql
Intellectual Property
C++
Public Speaking
Systems Engineering
Test Automation
Cloud Computing
Computer Architecture
Data Mining
Xml
Information Technology
Visual Basic
Information Security
Electrical Engineering
Matlab
System Architecture
Defense
Technical Analysis
Microelectronics
Visual Studio
Eclipse
Java Enterprise Edition
Scaled Agile Framework
Product Management
Safe
Interests:
Solving Problems Through Technology
Education
Playing the Piano
Science and Technology
Devouring Technological Information
Languages:
English
Awards:
The Army Commendation Medal
Department of the Army
For extraordinary achievement on 18 January 1989, while assigned to Foxtrot Company, 4th Aviation. The outstanding appearance, superior technical knowledge and exceptional military bearing of Specialist Cann distinguished him from the other competitors and earned him the Honor of the 4th Infantry Division (Mechanized) Soldier of the Year. This achievement is in keeping with the finest traditions of the Military and reflects great credit on himself, his unit and the United States Army.
The Army Commendation Medal
Department of the Army
For meritorious service to the Fort Carson and Colorado community while serving as the Aircraft Maintenance Platoon Sergeant for the 571st Medical Detachment. His demeanor, professionalism and dedication is a credit to himself, the unit and the United States Army.
The Army Achievement Medal
Department of the Army
For exceptionally meritorious service as soldier of the year 1988, for the Fourth Aviation Brigade. His military appearance and knowledge are the epitome of the outstanding soldiers we have in today's Army. Specialist Cann's efforts and initiative set an incomparable example to be emulated by all soldiers of the "Iron Eagle" Brigade. His performance has been exemplary in all aspects of each of his duties. Specialist Cann's meritorious performance of duty is in keeping with the highest traditions of military service and reflects great credit upon him, the Fourth Aviation Brigade, and the United States Army.
First Place, District 45, Division G, International Speech Contest
Toastmasters International
See attached speech, 'The Rules', in the 'Experience' section of my profile.
First Place, District 45, Division G, International Speech Contest
Toastmasters International
See attached speech, 'When To Let Go', in the 'Experience' section of my profile.
Certifications:
Top Secret Security Clearance (Ts/Ssbi)
Federal Aviation Administration (Faa) Airframe and Powerplant Mechanic (A&P)
Machine Learning, Stanford University
Certified Scrummaster (Csm)
Certified Scrum Product Owner (Cspo)
Sun Solaris System Administrator
Safe® 4 Certified Product Owner/Product Manager (Popm)
Certified Information Systems Security Professional (Cissp)
Sun Microsystems
United States Department of Defense
Us Department of Transportation (Dot)

Publications

Us Patents

Test Structure And Methodology For Three-Dimensional Semiconductor Structures

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US Patent:
8294149, Oct 23, 2012
Filed:
Nov 6, 2007
Appl. No.:
11/935724
Inventors:
Kerry Bernstein - Underhill VT, US
Jerome L. Cann - Jericho VT, US
Christopher M. Durham - Round Rock TX, US
Paul D. Kartschoke - Williston VT, US
Peter J. Klim - Austin TX, US
Donald L. Wheater - Hinesburg VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 23/58
US Classification:
257 48, 257E21531, 438 18
Abstract:
A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

Inspection Methods And Structures For Visualizing And/Or Detecting Specific Chip Structures

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US Patent:
20060071208, Apr 6, 2006
Filed:
Oct 4, 2004
Appl. No.:
10/711765
Inventors:
Jerome Cann - Jericho VT, US
Steven Holmes - Guilderland NY, US
Leendert Huisman - South Burlington VT, US
Cherie Kagan - Ossining NY, US
Leah Pastel - Essex VT, US
Paul Pastel - Essex VT, US
James Salimeno - Fairfax VT, US
David Vallett - Fairfax VT, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H01L 23/58
H01L 21/66
US Classification:
257048000, 438014000, 438016000, 438692000, 257758000
Abstract:
The present invention provides inspection methods and structures for facilitating the visualization and/or detection of specific chip structures. Optical or fluorescent labeling techniques are used to “stain” a specific chip structure for easier detection of the structure. Also, a temporary/sacrificial illuminating (e.g., fluorescent) film is added to the semiconductor process to facilitate the detection of a specific chip structure. Further, a specific chip structure is doped with a fluorescent material during the semiconductor process. A method of the present invention comprises: providing a first and a second material; processing the first material to form a portion of a semiconductor structure; and detecting a condition of the second material to determine whether processing of the first material is complete.

Test Structure And Methodology For Three-Dimensional Semiconductor Structures

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US Patent:
20120262197, Oct 18, 2012
Filed:
Jun 26, 2012
Appl. No.:
13/533191
Inventors:
Kerry Bernstein - Underhill VT, US
Jerome L. Cann - Jericho VT, US
Christopher M. Durham - Round Rock TX, US
Paul D. Kartschoke - Williston VT, US
Peter J. Klim - Austin TX, US
Donald L. Wheater - Hinesburg VT, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G01R 31/3187
G01R 1/067
G01R 31/00
G01R 31/02
US Classification:
3247503, 324537, 32475403, 32475601
Abstract:
A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

Test Structure And Methodology For Three-Dimensional Semiconductor Structures

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US Patent:
20120264241, Oct 18, 2012
Filed:
Jun 26, 2012
Appl. No.:
13/533188
Inventors:
Kerry Bernstein - Underhill VT, US
Jerome L. Cann - Jericho VT, US
Christopher M. Durham - Round Rock TX, US
Paul D. Kartschoke - Williston VT, US
Peter J. Klim - Austin TX, US
Donald L. Wheater - Hinesburg VT, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H01L 21/66
US Classification:
438 18, 257E21531
Abstract:
A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.
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Jerome L Cann from Nellysford, VA, age ~57 Get Report