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Jeremy Minnich Phones & Addresses

  • 1900 Quincy Way, Boise, ID 83706 (208) 422-9852
  • Minster, OH
  • Sidney, OH
  • Jarales, NM
  • Dickerson, MD
  • Belen, NM
  • Bosque, NM

Publications

Us Patents

Die Package Having An Adhesive Flow Restriction Area

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US Patent:
7491570, Feb 17, 2009
Filed:
Sep 1, 2004
Appl. No.:
10/930789
Inventors:
Bret K. Street - Meridian ID, US
James M. Derderian - Boise ID, US
Jeremy E. Minnich - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 29/72
US Classification:
438 64, 438112, 438116, 438118, 438127
Abstract:
A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element. A second embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches that extend from one edge of the transparent element to the other edge. A third embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches. A fourth embodiment has a transparent element with an adhesive flow restriction area formed as a protuberance. A fifth embodiment comprises a trench in the die. A sixth embodiment has a die with a plurality of trenches in the die as an adhesive flow restriction area. A seventh embodiment has a die with a protuberance.

Die Package Having An Adhesive Flow Restriction Area

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US Patent:
20050151272, Jul 14, 2005
Filed:
Jan 6, 2004
Appl. No.:
10/751441
Inventors:
Bret Street - Meridian ID, US
James Derderian - Boise ID, US
Jeremy Minnich - Boise ID, US
International Classification:
H01L031/0203
US Classification:
257787000
Abstract:
A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element. A second embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches that extend from one edge of the transparent element to the other edge. A third embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches. A fourth embodiment has a transparent element with an adhesive flow restriction area formed as a protuberance. A fifth embodiment comprises a trench in the die. A sixth embodiment has a die with a plurality of trenches in the die as an adhesive flow restriction area. A seventh embodiment has a die with a protuberance.

Die Package Having An Adhesive Flow Restriction Area

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US Patent:
20070114646, May 24, 2007
Filed:
Jan 18, 2007
Appl. No.:
11/654576
Inventors:
Bret Street - Meridian ID, US
James Derderian - Boise ID, US
Jeremy Minnich - Boise ID, US
International Classification:
H01L 23/02
US Classification:
257678000
Abstract:
A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element. A second embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches that extend from one edge of the transparent element to the other edge. A third embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches. A fourth embodiment has a transparent element with an adhesive flow restriction area formed as a protuberance. A fifth embodiment comprises a trench in the die. A sixth embodiment has a die with a plurality of trenches in the die as an adhesive flow restriction area. A seventh embodiment has a die with a protuberance.

Method For Substrate Moisture Ncf Voiding Elimination

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US Patent:
20210111132, Apr 15, 2021
Filed:
Dec 22, 2020
Appl. No.:
17/130086
Inventors:
- Boise ID, US
BENJAMIN L. MCCLAIN - Boise ID, US
JEREMY E. MINNICH - Boise ID, US
International Classification:
H01L 23/00
H01L 21/56
H01L 23/31
H01L 25/065
H01L 25/00
H01L 23/29
Abstract:
A semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes moisture impermeable layer. The assembly includes a first substrate and a second substrate electrically connected to a surface of the first substrate. The assembly includes a layer between the two substrates with the moisture impermeable layer between the layer and the surface of the first substrate. The layer may be non-conductive film, die attach film, capillary underfill, or the like. A portion of the surface of the first substrate may include a solder mask between the moisture impermeable layer and the first substrate. The moisture impermeable layer prevents, or at least inhibits, moisture within the first substrate from potentially creating voids in the layer. The moisture impermeably layer may be a polyimide, a polyimide-like material, an epoxy, an epoxy-acrylate, parylene, vinyltriethoxysilane, or combination thereof. The moisture impermeable layer may have a high electrical resistance.

Method For Substrate Moisture Ncf Voiding Elimination

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US Patent:
20190252330, Aug 15, 2019
Filed:
Feb 15, 2018
Appl. No.:
15/898004
Inventors:
- Boise ID, US
BENJAMIN L. MCCLAIN - Boise ID, US
JEREMY E. MINNICH - Boise ID, US
International Classification:
H01L 23/00
H01L 23/29
H01L 23/31
H01L 21/56
H01L 25/065
H01L 25/00
Abstract:
A semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes moisture impermeable layer. The assembly includes a first substrate and a second substrate electrically connected to a surface of the first substrate. The assembly includes a layer between the two substrates with the moisture impermeable layer between the layer and the surface of the first substrate. The layer may be non-conductive film, die attach film, capillary underfill, or the like. A portion of the surface of the first substrate may include a solder mask between the moisture impermeable layer and the first substrate. The moisture impermeable layer prevents, or at least inhibits, moisture within the first substrate from potentially creating voids in the layer. The moisture impermeably layer may be a polyimide, a polyimide-like material, an epoxy, an epoxy-acrylate, parylene, vinyltriethoxysilane, or combination thereof. The moisture impermeable layer may have a high electrical resistance.

Method For 3D Ink Jet Tcb Interconnect Control

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US Patent:
20190131272, May 2, 2019
Filed:
Oct 30, 2017
Appl. No.:
15/797900
Inventors:
- Boise ID, US
Benjamin L. McClain - Boise ID, US
C. Alexander Ernst - Boise ID, US
Jeremy E. Minnich - Boise ID, US
International Classification:
H01L 23/00
Abstract:
A semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a pillar. The semiconductor device assembly includes a semiconductor device disposed over another semiconductor device. At least one pillar extends from one semiconductor device towards a pad on the other semiconductor device. The barrier on the exterior of the pillar may be a standoff to control a bond line between the semiconductor devices. The barrier may reduce solder bridging and may prevent reliability and electromigration issues that can result from the IMC formation between the solder and copper portions of a pillar. The barrier may help align the pillar with a pad when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of the semiconductor devices. Windows or slots in the barrier may permit the expansion of solder in predetermined directions while preventing bridging in other directions.

Method For Solder Bridging Elimination For Bulk Solder C2S Interconnects

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US Patent:
20190067232, Feb 28, 2019
Filed:
Aug 31, 2017
Appl. No.:
15/692803
Inventors:
- Boise ID, US
BENJAMIN L. MCCLAIN - BOISE ID, US
JEREMY E. MINNICH - BOISE ID, US
ZHAOHUI MA - BOISE ID, US
International Classification:
H01L 23/00
H01L 21/033
Abstract:
A semiconductor device assembly that includes a semiconductor device positioned over a substrate with a number of electrical interconnections formed between the semiconductor device and the substrate. The surface of the substrate includes a plurality of discrete solder mask standoffs that extend towards the semiconductor device. A thermal compression bonding process is used to melt solder to form the electrical interconnects, which lowers the semiconductor device to contact and be supported by the plurality of discrete solder mask standoffs. The solder mask standoffs permit the application of a higher pressure during the bonding process than using traditional solder masks. The solder mask standoffs may have various polygonal or non-polygonal shapes and may be positioned in pattern to protect sensitive areas of the semiconductor device and/or the substrate. The solder mask standoffs may be an elongated shape that protects areas of the semiconductor device and/or substrate.

Methods And Systems For Inhibiting Bonding Materials From Contaminating A Semiconductor Processing Tool

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US Patent:
20190067238, Feb 28, 2019
Filed:
Aug 25, 2017
Appl. No.:
15/686963
Inventors:
- Boise ID, US
Jeremy E. Minnich - Boise ID, US
International Classification:
H01L 23/00
H01L 21/67
Abstract:
Methods and systems for inhibiting bonding materials from entering a vacuum system of a semiconductor processing tool are disclosed herein. A semiconductor processing tool configured in accordance with a particular embodiment includes a bondhead having a first port, a second port, a first channel fluidly coupled to the first port, and a second channel fluidly coupled to the second port. The first port and first channel together comprise a first opening extending through the bondhead, and the second port and second channel together comprise a second opening extending through the bondhead. The second opening at least partially surrounds the first opening. A first flow unit is coupled to the first port and is configured to withdraw air from the first opening. A second flow unit is coupled to the second port and is configured to provide fluid to or withdraw fluid from the second opening.
Jeremy E Minnich from Boise, ID, age ~46 Get Report