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Jeremy G Chatwin

from Santa Cruz, CA
Age ~56
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Also known as:
Jeremy Te Chatwin
Phone and address:
131 Getchell St, Santa Cruz, CA 95060
(831) 458-9189
Related to:
Lynn Higgins, 60
Connected to:
Alex J Chatwin, 46Carleen B Chatwin, 63Chancellor Chatwin, 32Derek R Chatwin, 43Shannon N Chaty, 31Chris Chatzidakis, 64Minas Chatzithomas, 45Anastasia Chatzka, 41Jean S Chatzky, 60John A Chatzky, 68

Jeremy Chatwin Phones & Addresses

  • 131 Getchell St, Santa Cruz, CA 95060 (831) 458-9189
  • 125 Felix St, Santa Cruz, CA 95060 (831) 458-9189

Resumes

Resumes

Jeremy Chatwin Photo 1

President

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Location:
Santa Cruz, CA
Industry:
Semiconductors
Work:
Mixed Signal Systems Inc.
President
Mixed Signal Systems Inc. Feb 1998 - Jan 2016
Staff Design Engineer
Gec Plessey Semiconductors 1990 - 1996
Design Engineer
Skills:
Mixed Signal
Asic
Ic
Analog
Semiconductors
Cmos
Verilog
Circuit Design
Analog Circuit Design
Electronics
Eda
Integrated Circuit Design
Pll
Simulations
Power Management
Physical Design
Rf
Low Power Design
Jeremy Chatwin Photo 2

Jeremy Chatwin

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Publications

Us Patents

System And Method For Utilizing A Phase Interpolator To Support A Data Transmission Procedure

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US Patent:
7817764, Oct 19, 2010
Filed:
Mar 30, 2007
Appl. No.:
11/731292
Inventors:
Jeremy Chatwin - Santa Cruz CA, US
Assignee:
Sony Corporation - Tokyo
International Classification:
H04L 7/00
US Classification:
375371, 375376
Abstract:
A system and method for effectively supporting a data transmission procedure includes a phase interpolator with a modular array of unit phase interpolators that each receives a respective input clock signal that is phase-shifted with respect to other input clock signals received by the remaining unit phase interpolators. The unit phase interpolators responsively generate corresponding UPI output signals that are summed together to produce a receiver clock signal. The phase interpolator receives a phase control word that includes a UPI selection segment and a UPI output-control segment. The phase interpolator utilizes the UPI selection segment to selectively activate pairs of the unit phase interpolators. The phase interpolator also utilizes the UPI output-control segment for controlling the UPI output signals to thereby adjust phase characteristics of the receiver clock signal.

System And Method For Implementing A Phase Detector To Support A Data Transmission Procedure

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US Patent:
7864911, Jan 4, 2011
Filed:
Jan 9, 2007
Appl. No.:
11/651323
Inventors:
Jeremy Chatwin - Santa Cruz CA, US
Assignee:
Sony Corporation - Tokyo
International Classification:
H03D 3/24
US Classification:
375375, 327244
Abstract:
A system and method for effectively supporting a data transmission procedure includes a phase-locked loop with a phase detector that compares a clock signal and input data to generate a phase error signal for adjusting the clock signal that is generated from a voltage-controlled oscillator. The phase detector includes a positive-edge detector circuit that generates an edge detection signal P to indicate whether data transitions are present in the input data. The phase detector also includes a lead/lag indicator circuit that generates a lead/lag indicator signal T to indicate whether the clock signal is early or late with respect to the input data.

System And Method For Implementing A Phase Detector To Support A Data Transmission Procedure

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US Patent:
8149980, Apr 3, 2012
Filed:
Nov 16, 2010
Appl. No.:
12/927483
Inventors:
Jeremy Chatwin - Santa Cruz CA, US
Assignee:
Sony Corporation - Tokyo
International Classification:
H03D 3/24
US Classification:
375375, 327244
Abstract:
A system and method for effectively supporting a data transmission procedure includes a phase-locked loop with a phase detector that compares a clock signal and input data to generate a phase error signal for adjusting the clock signal that is generated from a voltage-controlled oscillator. The phase detector includes a positive-edge detector circuit that generates an edge detection signal P to indicate whether data transitions are present in the input data. The phase detector also includes a lead/lag indicator circuit that generates a lead/lag indicator signal T to indicate whether the clock signal is early or late with respect to the input data.

System And Method For Effectively Implementing A Front End Core

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US Patent:
8274335, Sep 25, 2012
Filed:
Apr 14, 2011
Appl. No.:
13/066412
Inventors:
Jeremy Chatwin - Santa Cruz CA, US
Assignee:
Sony Corporation - Tokyo
International Classification:
H03F 3/08
US Classification:
330308, 330 98
Abstract:
An apparatus for implementing a front end core for a transimpedance amplifier includes an input transimpedance stage that receives an FE core input signal and responsively generates an output transimpedance gain signal. A first output gain stage receives the output transimpedance gain signal and responsively generates an FE core output signal. A phase inverter stage also receives the output transimpedance gain signal and responsively generates an inverted output signal. A second output gain stage then receives the inverted output signal and responsively generates an inverted FE core output signal.

System And Method For Effectively Implementing A Unit Gm Cell

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US Patent:
8314660, Nov 20, 2012
Filed:
Mar 29, 2011
Appl. No.:
13/065723
Inventors:
Jeremy Chatwin - Santa Cruz CA, US
Assignee:
Sony Corporation - Tokyo
International Classification:
H03F 3/08
US Classification:
330308, 330311
Abstract:
An apparatus and method for effectively implementing a unit Gm cell includes an input P that receives an input P signal and an input N that receives an input N signal. The unit Gm cell further includes an output P that generates an output P signal that is connected through a first bias resistor to the input N. The unit Gm cell also includes an output N that generates an output N signal that is connected through a second bias resistor to the input P. The unit Gm cell features level-shifting resistors that cause the output P signal and the output N signal to be at different respective voltage levels. A Vcore supply voltage may thus be reduced by a voltage potential across the level-shifting resistors to operate the unit Gm cell with a reduced Vcore supply voltage.

System And Method For Effectively Performing A Clock Signal Distribution Procedure

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US Patent:
8633776, Jan 21, 2014
Filed:
Sep 24, 2007
Appl. No.:
11/903710
Inventors:
Jeremy Chatwin - Santa Cruz CA, US
Bernard J. Griffiths - Ben Lomond CA, US
Assignee:
Sony Corporation - Tokyo
Sony Electronics Inc. - Park Ridge NJ
International Classification:
H03B 5/08
H03B 5/18
US Classification:
331167, 331 36 C, 331109, 331117 R, 331117 FE, 331177 V
Abstract:
A system and method for effectively performing a clock signal distribution procedure includes a clock generator configured to generate one or more clock signals that include electronic timing information. A clock load utilizes the electronic timing information from the clock signals to synchronize appropriate system processes. Capacitive coupling means are provided in a series configuration for transferring the clock signals from the clock generator to the clock load in accordance with an alternating-current direct-drive technique.

System And Method For Implementing A Dual-Mode Pll To Support A Data Transmission Procedure

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US Patent:
8208596, Jun 26, 2012
Filed:
Jul 16, 2007
Appl. No.:
11/879088
Inventors:
Jeremy Chatwin - Santa Cruz CA, US
Assignee:
Sony Corporation - Tokyo
Sony Electronics Inc. - Park Ridge NJ
International Classification:
H03D 3/24
US Classification:
375376, 375327, 375373, 375374, 331179, 331 17, 331 34
Abstract:
A system and method for effectively utilizing a dual-mode phase-locked loop to support a data transmission procedure includes a voltage controlled oscillator that generates a receiver clock signal in response to VCO input control signals. A binary phase detector generates a BPD output signal during a BPD mode by comparing input data and the receiver clock signal. In addition, a lock-assist circuit generates a PFD output signal during a PFD mode by comparing a reference signal and a divided receiver clock signal. A loop filter performs a BPD transfer function to generate a VCO input control signal from the BPD output signal during the BPD mode. The same loop filter also performs a PFD transfer function to generate the VCO input control signal from the PFD output signal during the PFD mode.

Stable Agc Transimpedance Amplifier With Expanded Dynamic Range

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US Patent:
20020101285, Aug 1, 2002
Filed:
Jul 20, 2001
Appl. No.:
09/910660
Inventors:
Jeremy Chatwin - Santa Cruz CA, US
International Classification:
H03F003/45
US Classification:
330/254000
Abstract:
Wide dynamic range and stability are achieved by adjusting a gain control resistance of an amplifier such that the pole ratio between the input and output is stable and by using a gain compensation technique to adjust output current. Adjustment of the gain is performed by determining a peak voltage between a gain stage and a dummy gain stage amplifier that does not amplify the input voltage. The peak voltage is compared to a gain control reference voltage and the comparison output is used to regulate both the variable gain and the gain compensation. The variable gain is performed using an FET variable resistor in a feed back loop of the amplifier. The gain compensation technique uses an FET variable resistor to adjust a voltage level of a driving transistor that adjusts an amount of current provided to an input of a current mirror. The mirrored current is then used to drain bias current from the amplifier.
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Jeremy G Chatwin from Santa Cruz, CA, age ~56 Get Report