Resumes
Resumes

Principle Design Engineer
View pageLocation:
San Francisco, CA
Industry:
Semiconductors
Work:
IDT since Sep 2004
Staff Design Engineer
Integrated Device Technology Inc since Sep 2004
Staff Design Engineer
Intel Corporation Nov 2003 - Sep 2004
Place and Route contractor
LSI Corporation Apr 2002 - Oct 2003
Senior Physical Design Engineer
Cadence Design Systems 1996 - 2001
Design Engineer
Staff Design Engineer
Integrated Device Technology Inc since Sep 2004
Staff Design Engineer
Intel Corporation Nov 2003 - Sep 2004
Place and Route contractor
LSI Corporation Apr 2002 - Oct 2003
Senior Physical Design Engineer
Cadence Design Systems 1996 - 2001
Design Engineer
Education:
Penn State University 1994 - 1996
Master of Science (MS), Electrical and Electronics Engineering
Master of Science (MS), Electrical and Electronics Engineering
Skills:
Asic
Physical Design
Place and Route
Ic
Soc
Timing Closure
Static Timing Analysis
Serdes
Signal Integrity
Floorplanning
Drc
Lvs
Clock Tree Synthesis
Physical Design
Place and Route
Ic
Soc
Timing Closure
Static Timing Analysis
Serdes
Signal Integrity
Floorplanning
Drc
Lvs
Clock Tree Synthesis
Languages:
Mandarin
