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Jeffrey J Ruedinger

from Rochester, MN
Age ~60
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Also known as:
Jeff Ruedinger
Phone and address:
2502 Oakridge Dr, Rochester, MN 55902
(507) 285-9009
Related to:
Richard F Krebs, 94Vincent A Ruedinger, 31Catherine Burghardt Ruedinger, 62Susan M Ruedinger, 58Thomas O Ruedinger, 85Katrina L RuedingerSharon D Ruedinger, 83
Connected to:
Fred K Ruedinger, 71Andrew J Ruedisueli, 51Jessica L Ruedrich, 33Cheria A Ruedy, 67Andrew Ruef, 38Lee Ruef, 83Patricia A Ruef, 88Willy J Ruefenacht, 80Dixie C Rueff, 67Katherine M Rueff, 39

Jeffrey Ruedinger Phones & Addresses

  • 2502 Oakridge Dr, Rochester, MN 55902 (507) 285-9009
  • Briarcliff Manor, NY
  • Merrillan, WI
  • 2502 Oakridge Dr SW, Rochester, MN 55902

Work

Company: Ibm Dec 2014 Position: Ddr4 phy design

Education

School / High School: University of Wisconsin- Madison, WI 1981 Specialities: BS ECE in Electrical and Computer Engineering

Skills

Digital design languages: VHDL • Verilog • DSL1 • BDL/S • BDL/CS
Analog design languages: Veri... • Verilog-AMS (wreal)
Programming lan... • C++ • Java • TCL • SystemVerilog • REXX • PowerPC assembler • HTML
Operating systems: Linux • AIX • Windows • VM • OS/Open
Verification: Event & cy... • hardware assisted simulation acceleratio... • environment definition & implementat... • test plan creation & execution
B... • RiscWatch • test plan creation & execution
U... • requirements definition & flow down ... • ReqPro)

Resumes

Resumes

Jeffrey Ruedinger Photo 1

Jeffrey Ruedinger Rochester, MN

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Work:
IBM

Dec 2014 to 2000
DDR4 PHY design
IBM
Rochester, MN
Jan 2014 to Nov 2014
Hardware emulation with OpenPower partner
IBM
Rochester, MN
May 2013 to Dec 2013
Silicon NanoPhotonics verification for test site
IBM
Rochester, MN
Oct 2012 to Apr 2013
Project G Architecture & Verification
IBM
Rochester, MN
Aug 2012 to Feb 2013
ASIC Design Center Customer Verification / US Government Trade Study
IBM
Rochester, MN
Feb 2011 to Jul 2012
"Project AM" Verification Team Lead
IBM
Rochester, MN
Aug 2009 to Jan 2011
BlueGene/Q Pervasive Team Lead
IBM
Rochester, MN
Jan 2005 to Jul 2009
TSAT Satellite Systems Architect
IBM
Rochester, MN
Nov 2004 to Dec 2004
Chip Set Documentation Team Lead
IBM
Rochester, MN
Feb 2002 to Oct 2004
CELL processor Team Lead
IBM
Rochester, MN
Sep 1993 to Jan 2002
Hardware Emulation Team Lead
IBM
Rochester, MN
Jul 1991 to Aug 1993
I/O designer of 64 bit PowerPC CPU
IBM Boeblingen Germany

Jun 1989 to Jun 1991
Switch design for CERN parallel processor
IBM Research
Yorktown Heights, NY
Jul 1987 to May 1989
RP3 parallel processor
IBM
Kingston, NY
1985 to 1987
Development of first ESCON Director
IBM
Kingston, NY
Jun 1984 to Jun 1985
Development of first ESCON Director
Education:
University of Wisconsin
Madison, WI
1981 to 1985
BS ECE in Electrical and Computer Engineering
University classes
1985
Continuing Education
Skills:
Digital design languages: VHDL, Verilog, DSL1, BDL/S, BDL/CS<br/>Analog design languages: Verilog-A, Verilog-AMS (wreal) <br/>Programming languages: C, C++, Java, TCL, SystemVerilog, REXX, PowerPC assembler, HTML<br/>Operating systems: Linux, AIX, Windows, VM, OS/Open<br/>Verification: Event & cycle simulation, hardware assisted simulation acceleration & emulation, environment definition & implementation, test plan creation & execution<br/>Bring up: CPU and ASIC environments, RiscWatch, test plan creation & execution<br/>US government interaction: bid & proposal process, requirements definition & flow down (DOORS, ReqPro)

Publications

Us Patents

Method For Partitioning A Netlist Into Multiple Clock Domains

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US Patent:
6523155, Feb 18, 2003
Filed:
Nov 17, 1998
Appl. No.:
09/193733
Inventors:
Jeffrey Joseph Ruedinger - Rochester MN, 55902
International Classification:
G06F 1750
US Classification:
716 7, 716 6, 703 23
Abstract:
A method partitions a netlist into multiple clock domains. The number of clock domains is the number of primary input clocks plus one freerun domain. First, each functional block in the netlist is colored with a number of colors corresponding to the number of primary input clocks. Buckets are then created, with one bucket corresponding to a particular clock domain. Each functional block in the netlist is then placed in one of the buckets according to one or more partition criterion, which takes into account the color of logic that feeds a functional block and the color of logic that the functional block feeds. The result is that the original netlist is partitioned into multiple netlists, each of which corresponds to a single clock domain. These multiple netlists may be executed in parallel to emulate the function of the circuit represented in the netlist.

Optical Fiber Transmission Bypass Device

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US Patent:
6647174, Nov 11, 2003
Filed:
Jan 8, 2002
Appl. No.:
10/041256
Inventors:
Thomas Michael Gooding - Rochester MN
Jeffrey Joseph Ruedinger - Rochester MN
Christopher Paul Schieffer - Rochester MN
Michael Arthur Snyder - Rochester MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G02B 626
US Classification:
385 18, 385 16, 385 23, 385 31, 398 2, 398 3, 398 7
Abstract:
An optical transmission bypass device attaching a network device to a fiber optic network allows fiber optic transmissions to bypass the network device when not powered, thereby maintaining continuity of the fiber network. A first and second actuating optical reflector has a reflective face that, in an un-powered state, is disposed to place the reflective face of the actuating optical reflector in a first position with respect to an optical path of an optical port, and, in a powered state, is disposed to place the reflective face of the actuating optical reflector in a second position with respect to the optical path of the optical port.

Non-Synchronous Hardware Emulator

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US Patent:
6832185, Dec 14, 2004
Filed:
Mar 9, 2000
Appl. No.:
09/522354
Inventors:
Roy Glenn Musselman - Rochester MN
Jeffrey Joseph Ruedinger - Rochester MN
Assignee:
Quickturn Design Systems, Inc. - San Jose CA
International Classification:
G06F 9455
US Classification:
703 23
Abstract:
A hardware emulator chip contains an array of cells and a programmable interconnection array. Each cell performs only a single logic function, which is configurable. The chips run asynchronously to one another, and within each chip cells are enabled by a sequential wave signal, which enables successive logical rows of cells. Within the chip, it is possible to connect any arbitrary cell output to any arbitrary cell input. Preferably, a set of off-chip connections is made possible by time-multiplexing the output of each subset to the wave signal. In one embodiment, full interconnection of cells within a chip is provided by providing a time-multiplexed programmable array of interconnect switches, the setting of each switch changing with each successive wave. In a second embodiment, full interconnection of cells within a chip is provided by providing a programmable array of interconnect switches. The hardware emulator described herein may thus be viewed as a hybrid of the FPGA type emulator and the time-multiplexed processor array emulator.

Time-Multiplexing Data Between Asynchronous Clock Domains Within Cycle Simulation And Emulation Environments

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US Patent:
6842728, Jan 11, 2005
Filed:
Mar 12, 2001
Appl. No.:
09/804210
Inventors:
Thomas Michael Gooding - Rochester MN, US
Roy Glenn Musselman - Rochester MN, US
Robert N Newshutz - Rochester MN, US
Jeffrey Joseph Ruedinger - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9455
US Classification:
703 23, 702125, 703 16, 703 19, 703 20, 703 25, 703 27, 712 29, 712 35, 712203, 712206, 712223, 712245, 713400, 716 6, 716 16
Abstract:
An apparatus and method utilize a buffer interposed in a common signal path between asynchronous clock domains in a hardware-based logic emulation environment to manage the communication of time-multiplexed data signals between the clock domains during hardware-based emulation. The buffer is effectively used to latch each data signal communicated across the common signal path so that the clock domain that receives the signals can retrieve each such signal at appropriate points in the receiver clock domain's evaluation cycle. Independently-controlled write/read pointers are maintained in a buffer control circuit to independently address the buffer for the transmitter and receiver sides of an asynchronous communication path. Locations in the buffer are associated with specific steps in the evaluation cycles of each of the transmitter and receiver clock domains, and the write/read pointers are managed to respectively write and read data to and from the locations in the buffer based upon the current evaluation steps being performed within the respective evaluation cycles of the transmitter and receiver clock domains.

Bus Interface Controller For Determining Access Counts

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US Patent:
7124257, Oct 17, 2006
Filed:
Dec 5, 2002
Appl. No.:
10/313682
Inventors:
Jeffrey Douglas Brown - Rochester MN, US
David John Krolak - Rochester MN, US
Jeffrey Joseph Ruedinger - Rochester MN, US
Scott Douglas Clark - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
US Classification:
711154, 711173, 711147, 711152, 711141, 710100
Abstract:
The present invention provides for an integrated circuit (IC) bus system. A local IC is coupled to a remote IC through a bus interface. A local memory is coupled to the local IC. A bus interface controller is employable to track data transfer requests from the remote IC for data address that are contained within at least one segment of the first partitioned memory range. The bus interface controller is further employable to stop the forwarding of a data transfer request generated within the local IC to the remote IC, if the memory segment count corresponding to the data address of the locally generated data transfer request equals zero.

Method And Apparatus For Implementing Data Mapping With Shuffle Algorithm

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US Patent:
7174398, Feb 6, 2007
Filed:
Jun 26, 2003
Appl. No.:
10/607360
Inventors:
Scott Douglas Clark - Rochester MN, US
Charles Ray Johns - Austin TX, US
Jeffrey Joseph Ruedinger - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 13/00
G06F 13/12
G06F 15/16
US Classification:
710 66, 710 65
Abstract:
A method and apparatus are provided for implementing data mapping using a shuffle algorithm. An output shuffler and an input shuffler convert a physical data group to a plurality of data subgroups. The physical data group includes a plurality of bits and each subgroup includes a subplurality of bits. The output shuffler performs an output shuffle sequence for providing a predefined output pattern of ordered subplurality data bits. The predefined output pattern of ordered subplurality data bits is applied to the input shuffler. The input shuffler performs a reverse shuffle sequence. For each shuffle transfer a number of first header bytes of a packet are located at a first one of a plurality of physical layer links. Both the output shuffler and the input shuffler are implemented with minimized logic required to keep a largest multiplexer as a 4-to-1 multiplexer, resulting in minimal area and power being used for implementing the shuffle sequence and reverse shuffle sequence.

Time Multiplexed Interface For Emulator System

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US Patent:
7464017, Dec 9, 2008
Filed:
Jan 14, 2005
Appl. No.:
11/035552
Inventors:
Jeffrey Joseph Ruedinger - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/455
US Classification:
703 23, 703 25, 717134, 717135, 717138
Abstract:
A method for emulating a hardware design by time division multiplexing data communicated between an emulator and a runtime assist unit (RTAU), such as a behavior card. Data from the emulator may be received directly at the general purpose registers of the RTAU. A programmable delay may be used in conjunction with a step generator to initiate concurrent cycle processes. Code executed by the RTAU may be coded in assembly, and external interrupts that might otherwise affect the determined processing time of the RTAU task are disabled. The time multiplexing reduces card port, cabling and processing cycle requirements.

Method And System For Ensuring Arbitration Fairness In Bus Ring Topology

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US Patent:
7551557, Jun 23, 2009
Filed:
Jun 19, 2003
Appl. No.:
10/464893
Inventors:
Scott Douglas Clark - Rochester MN, US
Jeffrey Joseph Ruedinger - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04L 12/54
US Classification:
370230, 370235, 370412, 370428
Abstract:
The present invention provides for dynamically determining a ratio of forwarded packets to injected packets to be transmitted in a bus ring. At least one forwarded packet is received into a first queue. An injected packet is received into a second queue. A determination, or snapshot, of the number of forwarded packets in the first queue due to the presence of the injected packet in the second queue is triggered. Packets corresponding to the snapshot are transmitted. After the packets are transmitted, if there is another injected packet stored in the second queue, another snapshot is performed. Packets corresponding to this snapshot are transmitted, and so on.
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Jeffrey J Ruedinger from Rochester, MN, age ~60 Get Report