Jeffrey R Biamonte

6977478, Dec 20, 2005

Apr 29, 2004

10/835138

Jeffrey R. Biamonte - Hyde Park NY, US
Timothy M. Trifilo - Walden NY, US

International Business Machines Corporation - Armonk NY

H02P001/42
H02P001/18
H02P001/34

318824, 318778, 318786, 318819, 318818

A controller is provided for transitioning a drive signal to a single phase motor between a square wave and pulse width modulation modes, wherein the drive signal is in square wave mode at low motor frequencies and in pulse width modulation mode during normal operation. The transitioning includes using a real time motor model to effectuate transition of the drive signal between the modes, and a sampling rate for sampling the real time motor model during the transitioning. The sampling rate is automatically modified during the transitioning, wherein acceleration of the motor includes transitioning the drive signal from square wave mode to pulse width modulation mode, including periodically increasing the sampling rate during the transitioning. Conversely, when transitioning from pulse width modulation mode to square wave mode, the controller automatically deaccelerates the sampling rate during the transitioning.

6995530, Feb 7, 2006

Apr 22, 2004

10/830348

Jeffrey R. Biamonte - Hyde Park NY, US
Raymond J. Harrington - Staatsburg NY, US
Timothy Trifilo - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

H02P 3/18

318254, 318138, 318439, 318459, 318500, 3889281

A system and a method for starting a brushless DC motor are provided. The method includes applying commutation pulses to at least two phase coils to induce a rotor to rotate to a starting position and then de-energizing the at least two phase coils. The method further includes applying commutation pulses to at least two phase coils to induce the rotor to rotate from the starting position in a predetermined direction. The method further includes de-energizing all phase coils for a first time interval after the rotor is rotating and sampling a back EMF signal in at least one of the phase coils to determine a first value indicative of an electrical period of the back EMF signal or a portion of an electrical period of the back EMF signal. Finally, the method includes applying commutation pulses to at least two phase coils for a second time interval, the second time interval being based on the first value.

7057414, Jun 6, 2006

Jan 7, 2004

10/752956

Daniel J. Barus - Glenham NY, US
Eileen M. Behrendt - Mahopac NY, US
Jeffrey R. Biamonte - Hyde Park NY, US
Raymond J. Harrington - Staatsburg NY, US
Timothy M. Trifilo - Walden NY, US

International Business Machines Corporation - Armonk NY

H03K 19/173

326 46, 326 86, 710 25

In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.

7088137, Aug 8, 2006

May 4, 2004

10/838391

Eileen M. Behrendt - Mahopac NY, US
Jeffrey R. Biamonte - Hyde Park NY, US
Raymond J. Harrington - Staatsburg NY, US
Timothy M. Trifilo - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

H03K 19/173
G06F 13/00

326 46, 326 86, 710 2, 710300, 710100, 710305, 710106

A communication system, method and program product are provided for establishing an extended bidirectional communication bus between a first device and a second device. The communication system includes decomposition logic for decomposing a single line, bidirectional data communication bus into a unidirectional transmit data communication bus and a unidirectional receive data communication bus. A differential communication subsystem is connected to the two unidirectional buses for extending the length thereof, and recomposition circuitry is connected to the differential communication subsystem for recombining the extended unidirectional transmit data communication bus and the extended unidirectional receive data communication bus to reestablish the single line, bidirectional data communication bus. The decomposition logic, differential communication subsystem and recomposition circuitry are implemented transparent to the first device and the second device and without use of a data direction control line.

7353308, Apr 1, 2008

Oct 20, 2005

11/254577

Daniel J. Barus - Glenham NY, US
Eileen M. Behrendt - Mahopac NY, US
Jeffrey R. Biamonte - Hyde Park NY, US
Raymond J. Harrington - Staatsburg NY, US
Timothy M. Trifilo - Walden NY, US

International Business Machines Corporation - Armonk NY

G06F 13/00

710110, 710104, 710118, 710305, 326 86, 326 46

In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.

7493433, Feb 17, 2009

Oct 29, 2004

10/977758

Eileen M. Behrendt - Mahopec NY, US
Jeffrey R. Biamonte - Hyde Park NY, US
Raymond J. Harrington - Staatsburg NY, US
Timothy M. Trifilo - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

G06F 13/00
G06F 13/42
G06F 13/14

710110, 710105

A method for data access via an inter-integrated circuit (I2C) protocol. The method includes receiving an I2C read command at an I2C slave device, where the I2C read command is from an I2C master device. The method also includes reading stored data from a storage device in response to receiving an I2C read command. The stored data is at a first location in the storage device corresponding to a value in a register array pointer in the I2C slave device. The stored data is transmitted to the I2C master device in response to the reading. The method also includes receiving an I2C write command at the I2C slave device, where the I2C write command is from the I2C master device and the write command includes master data and a slave device register address. The master data is written to the storage device in response to receiving the I2C write command, with the master data being written at a second location in the storage device corresponding to the slave device register address.

7522524, Apr 21, 2009

Apr 29, 2004

10/834799

Eileen M. Behrendt - Mahopac NY, US
Jeffrey R. Biamonte - Hyde Park NY, US
Raymond J. Harrington - Staatsburg NY, US

International Business Machines Corporation - Armonk NY

H04L 12/50

370235, 370360, 370397, 370399, 370409

One or more multiport systems are used to facilitate servicing of asynchronous communications events. A multiport system, such as an open collector multiport system, receives from one of a plurality of source components an asynchronous communications event directed to a target component coupled to the plurality of source components. The multiport system is controlled to provide, at any given time, a communications path between a plurality of ports of the multiport system to service the asynchronous communications event. One or more multiport systems are used to forward the event from the source to the target.

7983168, Jul 19, 2011

Apr 7, 2009

12/419719

Eileen M. Behrendt - Mahopac NY, US
Jeffrey R. Biamonte - Hyde Park NY, US
Raymond J. Harrington - Staatsburg NY, US

International Business Machines Corporation - Armonk NY

H04L 12/28

370235, 370360, 370400, 370437

One or more multiport systems are used to facilitate servicing of asynchronous communications events. A multiport system, such as an open collector multiport system, receives from one of a plurality of source components an asynchronous communications event directed to a target component coupled to the plurality of source components. The multiport system is controlled to provide, at any given time, a communications path between a plurality of ports of the multiport system to service the asynchronous communications event. One or more multiport systems are used to forward the event from the source to the target.