Jeffery C Brauch

6550023, Apr 15, 2003

Oct 19, 1998

09/175010

Jeffery C. Brauch - Fort Collins CO
Jay E. Fleischman - Fort Collins CO

Hewlett Packard Development Company, L.P. - Houston TX

G06F 1100

714 42, 714733, 714719, 714 57

A method and apparatus for locating defects in an on-chip memory of an integrated circuit is presented. During a memory test of on-chip memory, a known data value is written to a word in the on-chip memory, and an output data value is read back from the same addressed word in memory. A comparison of the output data value and expected data value is performed within the integrated circuit, producing a comparison result indicating which of the bit cells in the addressed word have failed. The address and comparison result are transferred external to said integrated circuit and correspond to a bitmap entry in a bitmap. The execution of a full memory test results in a complete bitmap indicating all the failed cells of the on-chip memory.

62984292, Oct 2, 2001

Sep 12, 2000

9/660032

Anne P. Scott - Fort Collins CO
Jeffery C Brauch - Ft Collins CO
Jay Fleischman - Fort Collins CO

Hewlett-Packard Company - Palo Alto CA

G06F 1206

711219

An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by defining a current memory address, choosing one or more modes by which increment-generated, decrement-generated, or combination increment/decrement addresses that define a next memory address are generated, and generating the row address and the column address of the next memory address in accordance with interdependent row carry-out and column carry-out operations.

63213206, Nov 20, 2001

Oct 30, 1998

9/183536

Jay Fleischman - Ft Collins CO
Jeffery C Brauch - Ft Collins CO
J. Michael Hill - Ft Collins CO

Hewlett-Packard Company - Palo Alto CA

G06F 1700

711217

A highly flexible and complex BIST engine provides at-speed access, testing, characterization, and monitoring of on-chip memory arrays, independent of other chip circuitry such as a CPU core. Each BIST engine has a main control block, at least one address generation block having an address local control block and one or more address-data generation blocks, and at least one data generation block having a data local control block and one or more data generation blocks. Each of the local address and data control blocks are programmed independently to define operations that will be performed by the individual address and data generation blocks, respectively. The main control block in turn controls operation of the local address and data control blocks to effect desired testing, accessing, and monitoring of the on-chip memory arrays.

57454191, Apr 28, 1998

Jul 30, 1996

8/690631

Jeffery C. Brauch - Fort Collins CO

Hewlett-Packard Co. - Palo Alto CA

G11C 2900

365201

Disclosed herein is a method of measuring the offset voltages of a plurality of SRAM sense amplifiers. The method comprises applying a series of stepped differential voltages to the plurality of sense amplifiers. After applying each differential voltage, an SRAM read operation is performed. The output of each sense amplifier may be interpreted with respect to the applied differential voltages. The point where a sense amplifier's output changes polarity will indicate a sense amplifier's offset voltage characteristic. Apparatus disclosed for implementing the method provides apparatus for isolating offset voltage test circuitry from other components of the SRAM while the SRAM is in a normal operating mode.

62494651, Jun 19, 2001

Feb 18, 2000

9/506620

Donald R Weiss - Ft Collins CO
Jay Fleischman - Ft Collins CO
Jeffery C Brauch - Ft Collins CO

Hewlett-Packard Company - Palo Alto CA

G11C 700
G11C 2900

365200

A system and method are disclosed which provide the capability of repairing an optimum number of defective memory segments, such as RAM segments, in order to minimize the amount of unused repairing circuitry, such as fuses used for repairing defects within the memory. A preferred embodiment of the present invention provides a RAM block implemented such that the number of fuses required for repairing defects therein is proportional to the optimum number of defective segments capable of being repaired. A preferred embodiment allows for repairing an optimum number of defective segments, while being capable of repairing any of the segments (up to the optimum number) by mapping repair data to an appropriate defective segment. A preferred embodiment provides a repairable RAM block comprising multiple segments of RAM memory cells that are each repairable, a state machine capable of generating repair data for repairing one or more defective segments, a scan address machine capable of generating data identifying one or more defective segments, and a mapping circuitry for mapping the generated repair data of the state machine to the one or more defective segments specified by the scan address machine. Accordingly, by providing the capability of mapping generated repair data to any one of the segments of RAM that is detected as being defective, a preferred embodiment enables repairing an optimum number of defective segments, without being required to provide sufficient circuitry for repairing every segment of RAM.

58963324, Apr 20, 1999

Dec 24, 1997

8/998420

Jeffery C. Brauch - Fort Collins CO

Hewlett-Packard Company - Palo Alto CA

G11C 700

365201

Disclosed herein is a method of measuring the offset voltages of a plurality of SRAM sense amplifiers. The method comprises applying a series of stepped differential voltages to the plurality of sense amplifiers. After applying each differential voltage, an SRAM read operation is performed. The output of each sense amplifier may be interpreted with respect to the applied differential voltages. The point where a sense amplifier's output changes polarity will indicate a sense amplifier's offset voltage characteristic. Apparatus disclosed for implementing the method provides apparatus for isolating offset voltage test circuitry from other components of the SRAM while the SRAM is in a normal operating mode.