Won Jee Kim

6427223, Jul 30, 2002

Apr 30, 1999

09/303181

Won Sub Kim - Fremont CA
John Harold Downey - San Jose CA
Daniel Marcos Chapiro - Palo Alto CA

Synopsys, Inc. - Mountain View CA

G06F 1750

716 4, 716 5, 716 6

The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the monitoring of a device under test (DUT). The HVL language supports Object-Oriented Programming (or OOP). Within this OOP framework, the present invention provides a monitoring facility comprised of three main stages: i) Coverage Definitions, ii) Coverage Instantiation and Triggering and iii) Coverage Feedback. A coverage definition is very similar to an OOP class definition, but does not contain methods or variables. Instead, the basic purpose of a coverage definition is to declare âmonitor binsâ in terms of a state variable. Essentially, each monitor bin declaration has a unique bin name which is associated with a particular behavior of the state variable and the unique bin name is used to record the state variables behavior. Instantiation of a coverage definition produces a coverage instance. Two key instantiation parameters are: an actual state variable that is to be monitored by the instance and a trigger expression which determines when the state variable of the instance is to be monitored.

6449745, Sep 10, 2002

Apr 22, 1999

09/298981

Won Sub Kim - Fremont CA
Mary Lynn Meyer - Mountain View CA
Daniel Marcos Chapiro - Palo Alto CA

Synopsys, Inc. - Mountainview CA

G01R 3128

714739, 714728

The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A ârandomizeâ method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. Because random variables may also appear on the right-hand-side (rhs) of a constraint expression there is an ordering in which random variable values must be assigned and this dependency is expressed by directed acyclic graphs (DAGs). A linear ordering for assigning values to the random variables is derived from the DAGs.

6493841, Dec 10, 2002

Mar 31, 1999

09/283774

Won Sub Kim - Fremont CA
Valeria Maria Bertacco - Stanford CA
Daniel Marcos Chapiro - Palo Alto CA
Sandro Hermann Pintz - Menlo Park CA

Synopsys, Inc. - Mountain View CA

G01R 3128

714741, 714739, 714 33, 703 17, 709310, 716 3

Hardware Verification Languages (HVLs) permit the convenient modeling of the environment for a device under test (DUT). HVLs permit the DUT to be tested by stimulating certain inputs of the DUT and monitoring the resulting states of the DUT. The present invention relates to an HVL, referred to as Vera, for the verification of any form of digital circuit design. Vera is preferably used for testing a DUT modeled in a high-level hardware description language (HLHDL) such as Verilog HDL. More specifically, the present invention relates to an HVL capability, know as an âexpect,â for monitoring the values at certain nodes of the DUT at certain times and for determining whether those values are in accordance with the DUTs expected performance. In particular, upon the first occurrence of a transition on one of the DUTs nodes, since beginning a window period of monitoring, the expect will either generate an error if the DUTs output is unexpected, or proceed with modeling the DUTs environment if the output is expected. A delay may be specified, which will delay the expects initiation of the window monitoring period.

6499127, Dec 24, 2002

Apr 22, 1999

09/298986

Won Sub Kim - Fremont CA
Mary Lynn Meyer - Mountain View CA
Daniel Marcos Chapiro - Palo Alto CA

Synopsys, Inc. - Mountain View CA

G01R 3128

714739, 714728

The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A ârandomizeâ method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. A constraint_expression can constrain any random variable which has been declared at its level in the class hierarchy, or at any higher level. A constraint_expression cannot constrain a random variable declared at a lower level in the hierarchy.

6513144, Jan 28, 2003

Apr 22, 1999

09/298984

Won Sub Kim - Fremont CA
Mary Lynn Meyer - Mountain View CA
Daniel Marcos Chapiro - Palo Alto CA

Synopsys, Inc. - Mountain View CA

G06F 1750

716 4, 716 18, 717108, 717116, 717126, 707103 Y, 703 2, 703 16, 703 22

The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A ârandomizeâ method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. If a constraint block of an instance is active or ON, then all the constraint expressions in the block will act to constrain their lhs random variable. A constraint block which is OFF means that all of its constraint expressions will not act to constrain their random variables.

6553531, Apr 22, 2003

Jun 24, 1999

09/344148

Won Sub Kim - Fremont CA
Mary Lynn Meyer - Mountain View CA
Daniel Marcos Chapiro - Palo Alto CA

Synopsys, Inc. - Mountain View CA

G01R 3128

714739

The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A ârandomizeâ method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions. The constraint expressions may impose a linear ordering in which random variable values must be assigned and this dependency is expressed by directed acyclic graphs (DAGs). The constraint expressions constraining each random variable are converted into ranges of permissible values from which a value is chosen at random. Rather than selecting a value for each random variable from within one of its ranges, as done for the randomize method, each boundary method call sequentially selects a combination of boundary values, for each random variable, from each random variables set of ranges.

6744590, Jun 1, 2004

May 16, 2001

09/859836

Sang Hoon Chu - Santa Clara CA
Ju Il Lee - San Jose CA
Jun Seok Shim - Cupertino CA
Won Goo Kim - San Jose CA

Samsung Electronics Co., Inc.

G11B 5596

360 7806, 360 7807, 318561

A method, apparatus, and computer program product for a hard disk drive servomechanism. In one embodiment, the apparatus comprises a disk which has a surface, a spindle motor that rotates the disk, a transducer which can write information onto the disk and read information from the disk, and an actuator arm that can move the transducer across the surface of the disk. The apparatus further includes a controller. The controller can determine a seek length from a first track to a second track, determine a seek time based on the seek length, scale the seek time in response to a velocity error between a calculated velocity and a design velocity for the seek length, and control the actuator arm to move the transducer across the disk surface from the first track to the second track using an acceleration trajectory.

7313583, Dec 25, 2007

Jun 12, 2003

10/460599

Joshua Porten - Palo Alto CA, US
Won Kim - Union City CA, US
Scott D. Johnson - Mountain View CA, US
John R. Nickolls - Los Altos CA, US

Broadcom Corporation - Irvine CA

G06F 15/00
H03M 13/00

708492, 714784

A Galois field arithmetic unit includes a Galois field multiplier section and a Galois field adder section. The Galois field multiplier section includes a plurality of Galois field multiplier arrays that perform a Galois field multiplication by multiplying, in accordance with a generating polynomial, a 1operand and a 2operand. The bit size of the 1and 2operands correspond to the bit size of a processor data path, where each of the Galois field multiplier arrays performs a portion of the Galois field multiplication by multiplying, in accordance with a corresponding portion of the generating polynomial, corresponding portions of the 1and 2operands. The bit size of the corresponding portions of the 1and 2operands corresponds to a symbol size of symbols of a coding scheme being implemented by the corresponding processor.